Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9530729-B2
Application number	US-201514859435-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Aug 30, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of pattern structures that are spaced apart from one another on a support layer and protrude from the support layer in a vertical direction, wherein the plurality of pattern structures comprise respective insulating spacers having an upper width smaller than a lower width;
a plurality of insulating extension patterns on the respective insulating spacers, wherein an upper width of the plurality of insulating extension patterns is greater than a lower width of the plurality of insulating extension patterns;
a plurality of contact patterns on the support layer between the plurality of pattern structures, wherein the plurality of contact patterns are spaced apart from the plurality of insulating extension patterns in the vertical direction; and
a plurality of conductive patterns on upper and lateral surfaces of respective ones of the plurality of pattern structures and electrically connected to respective ones of the plurality of contact patterns.

2. The semiconductor device of claim 1 , wherein each of the insulating spacers comprises a multi-layer spacer including an air spacer.

3. The semiconductor device of claim 1 , wherein each of the plurality of insulating extension patterns comprises an extension spacer.

4. The semiconductor device of claim 1 , wherein each of the plurality of insulating extension patterns is on upper portions of the respective ones of the plurality of pattern structures, and
wherein each of the plurality of conductive patterns separates the respective ones of the plurality of contact patterns from respective ones of the plurality of insulating extension patterns.

5. A semiconductor device comprising:
a plurality of word lines that extend on a substrate along a first direction and are spaced apart from one another in a second direction that is different from the first direction;
a plurality of bit line structures that extend in the second direction and are spaced apart from one another in the first direction;
a plurality of insulating spacers on respective ones of the plurality of bit line structures, wherein an upper width of the plurality of insulating spacers is smaller than a lower width of the plurality of insulating spacers;
a plurality of contact patterns spaced apart from one another on the substrate between the plurality of word lines and between the plurality of bit line structures;
a plurality of insulating extension spacers on respective ones of the plurality of insulating spacers, wherein an upper width of the plurality of insulating of insulating extension spacers is greater than a lower width of the plurality of insulating extension spacers; and
a plurality of conductive landing pads that are on upper and lateral surfaces of respective ones of the plurality of bit line structures, the respective ones of the plurality of insulating spacers, and respective ones of the plurality of extension spacers and are electrically connected to respective ones of the plurality of contact patterns, wherein the plurality of conductive landing pads are alternately on right and left sidewalls of each of the plurality of bit line structures along the second direction, and
wherein each of the plurality of conductive landing pads overlaps only a respective one of the plurality of bit line structures.

6. A semiconductor device comprising:
first and second pattern structures on a support layer, wherein the first and second pattern structures are spaced apart from each other in a first direction and extend in a second direction that is different from the first direction, wherein an upper width of the first and second pattern structures in the first direction is smaller than a lower width of the first and second pattern structures in the first direction, and wherein the first and second pattern structures protrude from the support layer in a vertical direction;
a plurality of extension patterns that extend on two sidewalls of each of the first and second pattern structures that extend in the second direction, wherein an upper width of the plurality of extension patterns in the first direction is greater than a lower width of the plurality of extension patterns in the first direction; and
a first conductive pattern that is on upper and lateral surfaces of the first pattern structure and is on upper and lateral surfaces of a first one of the plurality of extension patterns that is on one of the two sidewalls of the first pattern structure, wherein the first conductive pattern comprises a lower portion between the first and second pattern structures and an upper portion protruding from the lower portion in the vertical direction,
wherein the upper portion of the first conductive pattern extends on the lateral surface of the first pattern structure and overlaps the upper surface of the first pattern structure, and
wherein a portion of the upper portion of the first conductive pattern that extends on the lateral surface of the first pattern structure is spaced apart from a second one of the plurality of extension patterns that is on one of the two sidewalls of the second pattern structure facing the first pattern structure.

7. The semiconductor device of claim 6 , wherein each of the first and second pattern structures comprises a body conductive pattern and an insulation pattern on the body conductive pattern, and one of the plurality of extension patterns is on an upper portion of a sidewall of one of the insulation patterns.

8. The semiconductor device of claim 6 , wherein the first and second pattern structures comprise bit lines, and ones of the plurality of extension patterns comprise insulating spacers on respective sidewalls of the bit lines.

9. The semiconductor device of claim 6 , wherein the first and second pattern structures comprise bit lines, and wherein a buried contact is provided on the support layer between the bit lines and contacts the first conductive pattern.

10. The semiconductor device of claim 9 , wherein an uppermost surface of the buried contact is spaced apart from lowermost surfaces of the plurality of extension patterns in the vertical direction.

11. The semiconductor device of claim 9 , wherein the lower portion of the first conductive pattern contacts a lower surface of the first one of the plurality of extension patterns, and
wherein a width of the lower portion of the first conductive pattern in the first direction is equal to a width of the buried contact in the first direction.

12. The semiconductor device of claim 6 , further comprising a second conductive pattern that is on upper and lateral surfaces of the second pattern structure and is on upper and lateral surfaces of the second one of the plurality of extension patterns that is on the one of the two sidewalls of the second pattern structure, wherein the second conductive pattern is spaced apart from the first conductive pattern in the second direction,
wherein the second conductive pattern comprises a lower portion between the first and second pattern structures and an upper portion protruding from the lower portion of the second conductive pattern in the vertical direction,
wherein the upper portion of the second conductive pattern extends on the lateral surface of the second pattern structure and overlaps the upper surface of the second pattern structure, and
wherein a portion of the upper portion of the second conductive pattern that extends on the lateral surface of the second pattern structure is spaced apart from the first one of the plurality of extension patterns that is on the one of the two sidewalls of the first pattern structure.

13. The semiconductor device of cl

Assignees

• Choi Yong-Gyu
• Kim Hyun-Chul
• Ko Seung-Hee
• Samsung Electronics Co Ltd

Inventors

• Choi Yong-Gyu
• Kim Hyun-Chul
• Ko Seung-Hee

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/498 Primary

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10D64/011 Primary

  of electrodes ohmically coupled to a semiconductor · CPC title