Method for manufacturing semiconductor device with metal-containing film layer at bonding surface thereof

Patent metadata

Field	Value
Publication number	US-9716076-B2
Application number	US-201514827883-A
Country	US
Kind code	B2
Filing date	Aug 17, 2015
Priority date	Feb 14, 2012
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming an interlayer insulating layer on a semiconductor substrate;
forming a bonding electrode in a surface of the interlayer insulating layer such that the bonding electrode and the interlayer insulating layer define a bonding surface; and
forming a metal-containing film layer on an entirety of the bonding surface, wherein
the metal-containing film layer is processed to form an insulating film portion covering the interlayer insulating layer and a metal film portion covering the bonding electrode, and
the insulating film portion is a reaction product of a metal material of the metal-containing film layer with the interlayer insulating layer.

2. The method according to claim 1 , further comprising:
forming a barrier surface layer between the interlayer insulating layer and the bonding electrode.

3. The method according to claim 1 , wherein the metal-containing film layer includes at least one type selected from Ta or Ti.

4. The method according to claim 1 , wherein the bonding surface is a planar surface.

5. The method according to claim 1 , wherein a thickness of the metal-containing film layer is equal to or less than 100 nm.

6. The method according to claim 5 , wherein the thickness of the metal-containing film layer is equal to or less than 20 nm.

7. A method for manufacturing a semiconductor device including a first semiconductor substrate and a second semiconductor substrate, comprising:
forming a first interlayer insulating layer on the first semiconductor substrate;
forming a first bonding electrode in a surface of the first interlayer insulating layer such that the first bonding electrode and the first interlayer insulating layer define a first bonding surface;
forming a second interlayer insulating layer on the second semiconductor substrate;
forming a second bonding electrode in a surface of the second interlayer insulating layer such that the second bonding electrode and the second interlayer insulating layer define a second bonding surface; and
bonding the first semiconductor substrate to the second semiconductor substrate, including:
forming a first metal-containing film layer on the first bonding surface,
forming a second metal-containing film layer on the second bonding surface,
forming a first insulating film portion on the first interlayer insulating layer,
forming a second insulating film portion on the second interlayer insulating layer, and
laminating the first semiconductor substrate to the second semiconductor substrate, wherein

the first insulating film portion and the second insulating film portion include a reaction product between the first metal-containing film layer and the first interlayer insulating layer, and the second metal-containing film layer and the second interlayer insulating layer, respectively.

8. The method according to claim 7 , wherein the first metal-containing film layer is processed to form the first insulating film portion covering the first interlayer insulating layer and a metal film portion covering the first bonding electrode.

9. The method according to claim 7 , wherein the second metal-containing film layer is processed to form the second insulating film portion covering the second interlayer insulating layer and a metal film portion covering the second bonding electrode.

10. The method according to claim 7 , wherein the first metal-containing film layer is processed to form the first insulating portion covering the first interlayer insulating layer and a first metal film portion covering the first bonding electrode, and the second metal-containing film layer is processed to form the second insulating film portion covering the second interlayer insulating layer and a second metal film portion covering the second bonding electrode.

11. The method according to claim 7 , further comprising:
forming a barrier surface layer between the first interlayer insulating layer and the first bonding electrode, or between the second interlayer insulating layer and the second bonding electrode.

12. The method according to claim 7 , further comprising:
forming a first barrier surface layer between the first interlayer insulating layer and the first bonding electrode; and
forming a second barrier surface layer between the second interlayer insulating layer and the second bonding electrode.

13. The method according to claim 7 , wherein the first metal-containing film layer or the second metal-containing film layer includes at least one type selected from Ta or Ti.

14. The method according to claim 7 , wherein the first bonding surface and the second bonding surface are planar surfaces.

15. The method according to claim 7 , wherein a thickness of the first metal-containing film layer or a thickness of the second metal-containing film layer is equal to or less than 100 nm.

16. The method according to claim 7 , wherein a thickness of the first metal-containing film layer or a thickness of the second metal-containing film layer is equal to or less than 20 nm.

17. A method for manufacturing an electronic apparatus, comprising:
providing a semiconductor device, including:
forming an interlayer insulating layer on a semiconductor substrate,
forming a bonding electrode in a surface of the interlayer insulating layer such that the bonding electrode and the interlayer insulating layer define a bonding surface, and
forming a metal-containing film layer on an entirety of the bonding surface; and

providing a signal processing circuit which processes an output signal of the semiconductor device, wherein
the metal-containing film layer is processed to form an insulating film portion covering the interlayer insulating layer and a metal film portion covering the bonding electrode, and
the insulating film portion is a reaction product of a metal material of the metal-containing film layer with the interlayer insulating layer.

Assignees

• Sony Corp

Inventors

• Hagimoto Yoshiya
• Fujii Nobutoshi
• Aoyagi Kenichi

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W80/754

  having material changed during the connecting · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title