Flexible light emitting semiconductor device

Patent metadata

Field	Value
Publication number	US-9716061-B2
Application number	US-201213985096-A
Country	US
Kind code	B2
Filing date	Feb 17, 2012
Priority date	Feb 18, 2011
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A flexible polymeric dielectric layer has first and second major surfaces. The first major surface has a conductive layer thereon. The dielectric layer has at least one via extending from the second major surface to the first major surface. The conductive layer includes electrically separated first and second portions configured to support and electrically connect a light emitting semi-conductor device to the conductive layer.

First claim

What is claimed is:

1. An article comprising:
a flexible polymeric dielectric layer having first and second major surfaces, a first plane comprising the first major surface, the first major surface having a conductive layer directly thereon, the dielectric layer having at least one via extending from the second major surface to the first major surface, the conductive layer including electrically separated first and second portions, each of the first and second portions configured to support and electrically connect a light emitting semiconductor device to the conductive layer, at least some of the vias in the at least one via having sloped side walls, the sloped side walls having side wall angles from about 5 degrees to about 60 degrees from the first plane.

2. The article of claim 1 , further comprising a thermal interface material disposed in the at least one via.

3. The article of claim 1 further comprising a light emitting semiconductor device supported and electrically connected to the conductive layer on the first major surface by the first and second portions.

4. The article of claim 1 , wherein the first and second portions of the conductive layer on the first major surface are electrically separated by a gap, and further comprising a thermal interface material disposed in the gap.

5. A flexible article comprising:
a polymeric dielectric layer having a first major surface with a first electrically conductive layer directly thereon and having a second major surface, a first plane comprising the first major surface, a second plane comprising the second major surface, the dielectric layer disposed within a region between the first and second planes, the dielectric layer having at least one via extending from the second major surface to the first major surface, the first electrically conductive layer comprising an electrically conductive feature substantially aligned with the via, and a light emitting semiconductor device supported by the electrically conductive feature, the light emitting semiconductor device disposed outside the region between the first and second planes, wherein at least some of the vias in the at least one via have sloped side walls, the sloped side walls having side wall angles from about 5 degrees to about 60 degrees from the first plane.

6. The article of claim 5 , wherein the conductive feature comprises electrically separated first and second portions supporting and electrically connecting the light emitting semiconductor device to the conductive layer on the first major surface.

7. The article of claim 5 further comprising a second electrically conductive layer on the second major surface of the dielectric layer.

8. The article of claim 5 , wherein the at least one via contains thermally conductive material.

9. The article of claim 5 , further comprising a thermal interface layer abutting the second major surface and the thermally conductive material in the at least one via.

10. An article comprising:
a flexible dielectric layer having a first major surface with a first conductive layer directly thereon and having a second major surface, a first plane comprising the first major surface, the dielectric layer having at least one via extending from the second major surface to the first major surface, each via in the at least one via filled with conductive material, the first conductive layer comprising a conductive feature substantially aligned with the at least one via, and the first conductive layer further comprising conductive pads disposed adjacent the conductive feature, wherein at least some of the vias in the at least one via have sloped side walls, the sloped side walls having side wall angles from about 5 degrees to about 60 degrees from the first plane.

11. The article of claim 10 , wherein the at least one via comprises two vias, the first conductive layer comprising a conductive pad substantially aligned with each via.

Assignees

• Palaniswamy Ravi
• Jesudoss Arokiaraj
• Narag Alejandro Aldrin Il Agcaoili
• Foo Siang Sin
• Tan Fong Liang
• Pee Wei Meng
• Ouderkirk Andrew J
• Mooney Justine A
• 3M Innovative Properties Co

Inventors

• Palaniswamy Ravi
• Jesudoss Arokiaraj
• Narag Alejandro Aldrin Il Agcaoili
• Foo Siang Sin
• Tan Fong Liang
• Pee Wei Meng
• Ouderkirk Andrew J
• Mooney Justine A

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/662

  Semiconductor materials · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title