Sloped photoresist edges for defect reduction for metal dry etch processes

Patent metadata

Field	Value
Publication number	US-9716013-B2
Application number	US-201414172497-A
Country	US
Kind code	B2
Filing date	Feb 4, 2014
Priority date	Feb 4, 2014
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer.

First claim

The invention claimed is:

1. A method, comprising:
providing a substrate and a metal containing layer formed on a dielectric layer that is formed on a top semiconductor surface of said substrate;
forming a photoresist pattern from a photoresist layer formed on said metal containing layer including forming sloped edge regions of said photoresist pattern, said sloped edge regions having an average angle over a full length of said sloped edge regions of from ten (10) to fifty (50) degrees; and
dry etching said metal containing layer using said sloped edge regions of said photoresist pattern, wherein said sloped edge regions of said photoresist pattern reduce deposition and growth of an etch byproduct including said metal including material into sidewalls of said photoresist layer as compared to a vertical edge.

2. The method of claim 1 , wherein said metal including material is an elemental metal.

3. The method of claim 2 , wherein said elemental metal comprises molybdenum.

4. The method of claim 1 , wherein said metal including material is an elemental noble metal.

5. The method of claim 4 , wherein said elemental noble metal comprises platinum.

6. The method of claim 1 , wherein said metal including material is a metal alloy.

7. The method of claim 1 , wherein said metal including material is a metal compound including at least one non-metal.

8. The method of claim 1 , wherein said forming said sloped edge regions of said photoresist pattern comprises an exposure process.

9. The method of claim 8 , wherein said exposure process includes defocus including changing a depth of focus, baking at a temperature sufficient to flow said photoresist layer, or using a grayscale mask for said forming said photoresist pattern.

10. The method of claim 1 , wherein said dry etching comprises plasma etching using Ar/Cl 2 , Cl 2 /BCl 3 or Cl 2 /HBr gas.

11. The method of claim 1 , wherein said dielectric layer includes dielectric material that includes a doped glass.

12. The method of claim 11 , wherein said doped glass comprises a borophosphosilicate glass (BPSG).

13. A method, comprising:
providing a substrate and a platinum (Pt) layer formed on a dielectric layer that is formed on a top semiconductor surface of the substrate;
forming a photoresist pattern from a photoresist layer formed on said Pt layer including forming sloped edge regions of said photoresist pattern, said sloped edge regions having an average angle over a full length of said sloped edge regions of from ten (10) to fifty (50) degrees; and
plasma etching said Pt layer using said sloped edge regions of said photoresist pattern, wherein said sloped edge regions of said photoresist pattern reduce deposition and growth of a Pt/polymer containing etch byproduct on sidewalls of said photoresist pattern as compared to a vertical edge.

14. The method of claim 13 , wherein said dielectric material comprises borophosphosilicate glass (BPSG).

Assignees

• Texas Instruments Inc

Inventors

• Stewart Elizabeth Costner
• Jiang Neng
• Chang Yung Shan
• Jackson Ricky Alan

Classifications

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P50/267 Primary

  using plasmas · CPC title

• H01L21/32136 Primary

  Electricity · mapped topic

• H01L21/32139

  Electricity · mapped topic