Stacked graphene field-effect transistor
US-2016204204-A1 · Jul 14, 2016 · US
US9714988B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9714988-B2 |
| Application number | US-201414514415-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 15, 2014 |
| Priority date | Oct 16, 2013 |
| Publication date | Jul 25, 2017 |
| Grant date | Jul 25, 2017 |
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A Hall Effect sensor with a graphene detection layer implemented in a variety of geometries, including the possibility of a so-called “full 3-d” Hall sensor, with the option for integration in a BiCMOS process and a method for producing said Hall Effect sensor is disclosed.
Opening claim text (preview).
What is claimed is: 1. A structure, comprising: a substrate having a first side; an epitaxy layer formed on said first side; a three-dimensional recess formed in the epitaxy layer; a seed layer formed on said first side; a graphene layer formed over at least a part of the seed layer; wherein at least a portion of the seed layer between the substrate and said graphene layer is removed without separating the substrate to form a suspended graphene structure from said graphene layer, a support structure formed over a portion of the graphene layer; and an encapsulation structure formed over a portion of the support structure; wherein the encapsulation structure, the support structure, and the graphene layer encloses a volume. 2. The structure of claim 1 , wherein the volume is capable of sustaining a low-pressure environment. 3. The structure of claim 1 , wherein the encapsulation structure completely fills said volume. 4. The structure of claim 1 , said encapsulation layer comprises borophosphosilicate glass. 5. The structure of claim 1 , wherein said encapsulation layer comprises high-density polyethylene. 6. A method for producing a hall sensor, comprising: providing a substrate having a first side; forming an epitaxy layer on said first side; forming a three-dimensional recess in the epitaxy layer; forming a seed layer on said first side after forming the three-dimensional recess; forming a graphene layer over at least a part of the seed layer without contacting the substrate; and removing a portion of the seed layer between the substrate and said graphene layer. 7. The method of claim 6 further comprising patterning the graphene layer. 8. The method of claim 6 wherein said portion of the seed layer is removed by etching. 9. The method of claim 8 wherein the portion of the seed layer which is not removed by etching forms at least one contact pad. 10. The method of claim 6 wherein the three-dimensional recess is formed on the (1,1,1) lattice plane. 11. The method of claim 6 wherein the three-dimensional recess is substantially pyramid shaped. 12. The method of claim 6 wherein the three-dimensional recess is substantially octagon shaped. 13. The method of claim 6 wherein the three-dimensional recess is substantially cube shaped. 14. The method of claim 6 wherein the three-dimensional recess is substantially quatrefoil shaped. 15. The method of claim 6 wherein the seed layer comprises a metal layer. 16. The method of claim 15 wherein the metal layer comprises copper. 17. The method of claim 15 wherein the metal layer comprises nickel. 18. The method of claim 15 wherein the metal layer comprises a copper-nickel alloy. 19. The method of claim 6 further comprising: forming an encapsulation layer over or around at least a portion of the graphene layer. 20. The method of claim 19 wherein said encapsulation layer comprises borophosphosilicate glass. 21. The method of claim 19 wherein said encapsulation layer comprises high-density polyethylene. 22. A hall sensor, comprising: a substrate having a first side; a seed layer formed on said first side, the seed layer comprising at least a first portion, a second portion and a third portion, each of the first, second and third portions of the seed layer being separated from respective other portions of the seed layer; and a graphene layer formed above the first, second and third portions of the seed layer and in contact with the first, second and third portions of the seed layer; wherein a further portion of the seed layer is removed between the substrate and said graphene layer to form a suspended graphene structure. 23. The hall sensor of claim 22 , wherein at least one wire is connected to each portion of the seed layer. 24. The hall sensor of claim 22 , wherein a stress-reducing mounting structure is arranged between the graphene layer and at least one of the portions of the seed layer.
Electricity · mapped topic
Manufacturing aspects; Manufacturing of single devices, i.e. of semiconductor magnetic sensor chips (devices based on galvano-magnetic effect or the like H10N50/85) · CPC title
Electricity · mapped topic
Constructional adaptation of the sensor to specific applications · CPC title
Electricity · mapped topic
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