Method of manufacturing a dual mode ferroelectric random access memory (FRAM) having imprinted read-only (RO) data

Patent metadata

Field	Value
Publication number	US-9711715-B2
Application number	US-201615189114-A
Country	US
Kind code	B2
Filing date	Jun 22, 2016
Priority date	Jun 11, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Read-only (“RO”) data to be permanently imprinted in storage cells of a memory array are written to the memory array. One or more over-stress conditions such as heat, over-voltage, over-current and/or mechanical stress are then applied to the memory array or to individual storage cells within the memory array. The over-stress condition(s) act upon one or more state-determining elements of the storage cells to imprint the RO data. The over-stress condition permanently alters a value of a state-determining property of the state-determining element without incapacitating normal operation of the storage cell. The altered value of the state-determining property biases the cell according to the state of the RO data bit. The bias is detectable in the cell read-out signal. A pre-written ferroelectric random-access memory (“FRAM”) array is baked. Baking traps electric dipoles oriented in a direction corresponding to a state of the pre-written data and forms am RO data imprint.

First claim

What is claimed is:

1. A method of manufacturing a dual mode memory array capable of storing an imprinted read-only (“RO”) data bit and a non-imprinted read/write (“R/W”) data bit per array storage cell, comprising:
writing RO data to be imprinted to at least one storage cell of the memory array; and
applying at least one over-stress condition to at least one state-determining element of the storage cell in order to imprint the storage cell with the RO data by permanently modifying a value of a state-determining property associated with the state-determining element and to thereby bias a magnitude of a read-out signal associated with at least one state of imprinted RO data;
performing a plurality of RO mode read operations on at least one imprinted cell to determine, for each RO mode read operation, an apparent state of the RO data imprinted in the at least one imprinted cell;
after each RO mode read operation, comparing the RO data written to the apparent state of the RO data imprinted in the at least one imprinted cell as read;
calculating an RO data read reliability by performing an averaging operation on the compared RO data; and
determining whether the RO data read reliability of the at least one imprinted cell is greater than or equal to a selected level.

2. The method of manufacturing a dual mode memory array of claim 1 , further comprising:
performing at least one additional over-stress operation if the RO data read reliability is less than the selected level; and
performing additional cycles of testing and over-stress operations until the RO data read reliability is greater than or equal to the selected level.

3. The method of manufacturing a dual mode memory array of claim 1 , each RO mode read operation comprising:
sensing a magnitude of an output signal associated with the at least one imprinted cell during the read operation;
comparing the sensed magnitude of the output signal of the at least one imprinted cell to an expected magnitude associated with an output of a non-imprinted storage cell;
determining whether a difference between an absolute value of the sensed magnitude and an absolute value of the expected magnitude is less than a selected amount;
interpreting a state of the RO data as a state associated with a polarity of the output signal during the read operation if the difference between the absolute values of the sensed magnitude and the expected magnitude is less than the selected amount; and
interpreting the state of the RO data as a state opposite that associated with a polarity of the output signal during the read operation if the difference between the absolute values of the sensed magnitude and the expected magnitude is greater than or equal to the selected amount.

4. A method of manufacturing a dual mode double cell (2T/2C) ferroelectric random access memory (FRAM) array capable of storing an imprinted read-only (“RO”) data bit and a non-imprinted read/write (“R/W”) data bit per array storage cell, comprising:
performing full-cell writes of RO data to be imprinted to storage cells of the dual mode double cell (2T/2C) FRAM array; and
baking the dual mode double cell (2T/2C) FRAM array at a selected temperature for a selected period of time to imprint the RO data to the storage cells;
conducting a test procedure, the test procedure comprising:
performing a plurality of RO mode read operations on at least one imprinted cell to determine, for each RO mode read operation, an apparent state of the RO data imprinted in the at least one imprinted cell;
after each RO mode read operation, comparing the RO data written to the apparent state of the imprinted RO data as read;
calculating an RO data read reliability by performing an averaging operation on the compared RO data; and
determining whether the RO data read reliability of the at least one imprinted cell is greater than or equal to a selected level.

5. The method of manufacturing a dual mode double cell (2T/2C) FRAM array of claim 4 , further comprising:
re-writing the RO data;
performing at least one additional baking cycle if the RO data read reliability of a selected number of imprinted FRAM cells is less than a selected minimum RO mode read reliability; and
performing additional cycles of testing and baking until the RO data read reliability of the selected number of imprinted FRAM cells is greater than or equal to the selected minimum RO mode read reliability.

6. The method of manufacturing a dual mode double cell (2T/2C) FRAM array of claim 4 , each of the plurality of RO mode read operations further comprising:
writing each of two half-cells of a FRAM storage cell from which the imprinted RO data is to be read with a pre-determined bit state;
sensing a polarity of a voltage difference between bit lines of the two half-cells during a full-cell read operation; and
interpreting an apparent state of the RO data bit imprinted in the FRAM storage cell according to the voltage difference.

7. The method of manufacturing a dual mode double cell (2T/2C) FRAM array of claim 6 , the writing of each half-cell with a pre-determined bit state further comprising:
performing a selected one of a group of operations consisting of successive half-cell writes of the pre-determined bit state to each half-cell and simultaneous writes of the pre-determined bit state to each half-cell.

8. The method of manufacturing a dual mode double cell (2T/2C) FRAM array of claim 6 , each of the plurality of RO mode read operations further comprising:
selecting a sense amplifier biased to sense a polarity of a decreased-magnitude voltage difference between the bit lines of the two half-cells of the imprinted FRAM cell.

9. The method of manufacturing a dual mode double cell (2T/2C) FRAM array of claim 6 , each of the plurality of RO mode read operations further comprising:
selecting a sense amplifier to sense a polarity of a voltage difference between the bit lines of the two half-cells of the imprinted FRAM cell, the sense amplifier biased to a common mode voltage of the voltage difference.

Assignees

• Texas Instruments Inc

Inventors

• Juvekar Chiraag
• Kwong Joyce
• Bittlestone Clive
• Ramaswamy Srinath
• Heinrich-Barna Stephen

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• G11C2211/4013

  Memory devices with multiple cells per bit, e.g. twin-cells · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title