Double patterning method

Patent metadata

Field	Value
Publication number	US-9240346-B2
Application number	US-201313920201-A
Country	US
Kind code	B2
Filing date	Jun 18, 2013
Priority date	Mar 14, 2013
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

Self-aligned double patterning methods that can be used in back-end-of-line (BEOL) processing and other stages of integrate circuit device manufacturing. In these methods, line termini are masked prior to self-aligned double patterning. The self-aligned double patterning involves forming a mandrel, the shape of which is determined by a lithographic mask. That same lithographic mask is used prior to self-aligned double patterning to trim the mask that determines the locations of line termini. The methods provide precise positioning of the line termini mask relative to the line locations determined by self-aligned double patterning. The methods forms consistent end-of-line shapes and allow line termini to be placed more closely together than would otherwise be feasible.

First claim

The invention claimed is:

1. A method of forming an integrated circuit device, comprising:
forming a first hard mask layer over a substrate;
forming a second hard mask layer over the first hard mask layer;
forming a first photoresist layer over the first and second hard mask layers;
exposing the first photoresist layer through a mandrel mask;
developing the first photoresist layer to form a mask;
patterning the second hard mask layer to form a second layer mask that defines locations at which conductive lines that will be formed in the substrate will end, wherein patterning comprises etching the second hard mask layer using the first photoresist layer as a mask and the first hard mask layer as an etch stop layer;
performing a self-aligned double-patterning of the first hard mask layer to form a first layer mask, wherein the first layer mask defines the locations at which the conductive lines will be formed in the substrate, wherein the first layer mask remains intact where it is masked by the second layer mask, and wherein performing the self-aligned double-patterning comprises forming a mandrel over the patterned second hard mask layer using the mandrel mask and subsequently etching the first hard mask layer;
forming trenches in the substrate by etching with the first layer mask providing a mask; and
filling the trenches with conductive metal to form the conductive lines.

2. The method of claim 1 , wherein:
there is a first ratio between the width of openings in the mandrel mask and the width of corresponding areas of the first photoresist layer that are affected by exposure through the mandrel mask;
there is a second ratio between the width of the openings in the mandrel mask and the width of corresponding features of the mandrel; and
the first ratio is significantly greater than the second ratio.

3. The method of claim 1 , wherein:
the widths of areas of the first photoresist layer that are affected by exposure through the mandrel mask is greater than the widths of corresponding features of the mandrel; and
the differences in the widths are greater than or equal to the uncertainty in alignment between the mandrel mask and the substrate.

4. The method of claim 1 , wherein the first photoresist layer is a negative photoresist.

5. The method of claim 1 , wherein the self-aligned double-patterning is performed after patterning the second hard mask layer, and wherein the self-aligned double-patterning comprises:
forming the mandrel;
forming spacers on sides of the mandrel; and
stripping the mandrel.

6. The method of claim 5 , further comprising:
prior to forming the spacers, forming narrow gaps in the mandrel;
wherein the spacers form in the gaps and span the gaps.

7. The method of claim 1 , wherein the second hard mask layer is patterned to define the locations at which the conductive lines will end and subsequently trimmed using the mask formed from the first photoresist layer.

8. The method of claim 1 , wherein:
the widths of some of the trenches correspond to the widths of features in the mandrel;
the widths of some others of the trenches correspond to the distances between adjacent spacers; and
the second hard mask layer determines the endpoints of some of the trenches.

9. A method of forming an integrated circuit device, comprising:
forming a first hard mask layer over a substrate;
forming a second hard mask layer over the first hard mask layer;
patterning the second hard mask layer to form islands, wherein patterning the second hard mask layer comprises initially etching the second hard mask layer according to a termini mask and subsequently etching the second hard mask layer according a mandrel mask to trim the second hard mask layer; and
performing a self-aligned double-patterning of the first hard mask layer using the patterned second hard mask layer, wherein the self-aligned double-patterning comprises forming a mandrel over the patterned second hard mask layer using the mandrel mask and forming line-shaped openings in the first hard mask layer, and wherein the islands mask termini of the line-shaped openings.

10. The method of claim 1 , wherein performing the self-aligned double-patterning of the first hard mask layer, comprises:
forming a sacrificial hard mask layer over the first mask hard layer and the patterned second hard mask layer;
patterning a second photoresist layer overlying the second hard mask layer to form the mandrel;
forming spacers on sides of the mandrel;
removing the mandrel; and
etching through the first hard mask layer with the remaining second hard mask layer and the spacers.

11. The method of claim 1 , wherein the trenches extend into a dielectric layer of the substrate.

12. A method of forming an integrated circuit device, comprising:
forming a first hard mask layer over a substrate;
forming a second hard mask layer over the first hard mask layer;
forming a photoresist layer over the first and second hard mask layers;
exposing the photoresist layer through a mandrel mask;
developing the photoresist layer to form a mask, the mask comprising a line-shaped feature with a first width;
patterning the second hard mask layer to form a second layer mask that defines locations at which conductive lines that will be formed in the substrate will end, wherein patterning the second hard mask layer comprises etching the second hard mask layer using the photoresist layer as a mask and the first hard mask layer as an etch stop layer;
after patterning the second hard mask layer, performing a self-aligned double-patterning of the first hard mask layer to form a first layer mask, wherein the first layer mask defines the locations at which the conductive lines will be formed in the substrate, wherein the first hard mask layer remains intact where it is masked by the second layer mask, and wherein performing the self-aligned double-patterning comprises forming a mandrel over the second mask layer using the mandrel mask and subsequently etching the first hard mask layer, wherein the mandrel has a second width different than the first width;
forming trenches in the substrate by etching with the first layer mask providing a mask; and
filling the trenches with conductive metal to form the conductive lines.

13. The method according to claim 12 , wherein the substrate comprises a semiconductor body and an overlying dielectric layer, and wherein the trenches are formed over the semiconductor body in the dielectric layer.

14. The method according to claim 12 , wherein performing the self-aligned double patterning further comprises:
forming a sacrificial hard mask layer over the first hard mask layer and the patterned second hard mask layer;
patterning the sacrificial hard mask layer to form the mandrel by processes that include exposing a second photoresist layer through the mandrel mask;
forming spacers on sides of the mandrel;
removing the mandrel; and
etching through the first hard mask layer with the remaining second hard mask layer and the spacers as masks.

15. The method of claim 14 , wherein forming spacers on sides of the mandrel comprises:
depositing a spacer material over the mandrel; and
etching the spacer material to form spacers on the sides of the mandrel.

16. The method of claim 15 , further comprising:
prior to depositing the spacer material, performing an additional masked etch to form gaps in the mandrel; and
wherein the gaps are sufficiently narrow that etching the spacer material to form spacers leaves the spacer material spanning the gaps.

17. The method of claim 12 , furth

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Chia-Ying
• Shieh Jyu-Horng

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title