Direct plasma densification process and semiconductor devices

Patent metadata

Field	Value
Publication number	US-9711399-B2
Application number	US-201315100531-A
Country	US
Kind code	B2
Filing date	Dec 26, 2013
Priority date	Dec 26, 2013
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.

First claim

What is claimed is:

1. A method of forming a barrier layer on a semiconductor device, comprising:
placing a substrate into a reaction chamber;
depositing a high-k dielectric layer on said substrate;
depositing a barrier layer on said substrate such that said high-k dielectric layer is between said barrier layer and said substrate, wherein said barrier layer includes a metal and a non-metal and said barrier layer exhibits an as-deposited thickness of 4 nm or less;
densifying said barrier layer by forming plasma from a gas proximate to said barrier layer so as to reduce the thickness of said barrier layer to a thickness in the range of 50 percent to 95 percent of the as-deposited thickness;
depositing a metal layer over said barrier layer.

2. The method of claim 1 , further comprising applying 300 Watts or less of power to said plasma at a frequency of 350 kHz to 40 MHz.

3. The method of claim 1 , further comprising depositing a metal layer before depositing said barrier layer.

4. The method of claim 3 , wherein said metal layer comprises titanium and said barrier layer comprises titanium nitride.

5. The method of claim 1 , where said barrier layer is deposited by supplying one or more reactive gas precursors to said reaction chamber.

6. The method of claim 5 , wherein said reactive gas precursor comprises tetrakis(dimethylamido)titanium.

7. The method of claim 6 , wherein said barrier layer comprises titanium, nitrogen and carbon.

8. The method of claim 6 , wherein said barrier layer comprises carbon present in the range of 1 atomic percent to 30 atomic percent, titanium present in the range of 20 atomic percent to 80 atomic percent and titanium nitride present in the range of 20 atomic percent to 80 atomic percent of the total atomic percent of the barrier layer.

9. The method of claim 1 , wherein said substrate is heated at a temperature in the range of 325° C. to 450° C. while densifying said barrier layer.

10. The method of claim 1 , wherein said metal layer comprises tungsten.

11. The method of claim 1 , wherein said metal layer comprises copper.

12. A method of forming a barrier layer on a semiconductor device, comprising:
placing a substrate into a reaction chamber;
depositing a titanium layer on said substrate;
depositing a titanium nitride barrier layer over said titanium layer, wherein said titanium nitride barrier layer is deposited at a thickness of 4 nanometers (nm) or less;
densifying said barrier layer by exposing the titanium nitride barrier layer to a plasma for a time ranging from about 100 to about 1000 seconds, wherein said plasma is formed from a gas supplied to said reaction chamber and 300 Watts or less of power at a frequency in the range of 350 kHz to 40 MHz is applied to the plasma so as to reduce the thickness and increase the density of said titanium nitride barrier layer; and
following said densification, a depth of nitrogen penetration from said titanium nitride barrier layer into said titanium layer is less than 5 nanometers (nm).

13. The method of claim 12 , wherein said titanium nitride layer is deposited using tetrakis(dimethylamido)titanium precursor.

14. The method of claim 12 , wherein said barrier layer comprises carbon present in the range of 1 atomic percent to 30 atomic percent, titanium present in the range of 20 atomic percent to 80 atomic percent and titanium nitride present in the range of 20 atomic percent to 80 atomic percent of the total atomic percent of the barrier layer.

15. The method of claim 12 , wherein said substrate includes a fin projecting from said substrate.

16. The method of claim 12 , further comprising depositing a metal over said titanium nitride barrier layer, wherein said metal is tungsten.

17. The method of claim 12 , further comprising depositing a metal over said titanium nitride barrier layer, wherein said metal comprises copper.

Assignees

• Intel Corp

Inventors

• Farmer Jason A
• Leib Jeffrey S
• Bergstrom Daniel B

Classifications

• H10P14/432

  using selective deposition · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/055

  by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition · CPC title

• H10W20/43

  Layouts of interconnections · CPC title