Shadow trim line edge roughness reduction

US9711359B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9711359-B2
Application numberUS-201514826088-A
CountryUS
Kind codeB2
Filing dateAug 13, 2015
Priority dateAug 13, 2015
Publication dateJul 18, 2017
Grant dateJul 18, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned organic mask. The mask layer is selectively etched with respect to the silicon based sidewalls or spacers, wherein the selectively etching the mask layer undercuts the silicon based sidewalls or spacers. The etch layer is selectively etched with respect to the mask layer. The stack and substrate are removed from the support and the plasma chamber.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for etching a silicon or metal based etch layer in a stack over a substrate wherein the etch layer is under a carbon based mask layer which is under a patterned organic mask, comprising: placing the stack and substrate on a support in the plasma chamber; in situ depositing a silicon based layer over the stack, wherein the silicon based layer is a silicon oxide or silicon nitride based layer; etching the silicon based layer to form silicon based sidewalls or spacers on sides of the patterned organic mask; selectively etching the carbon based mask layer with respect to the silicon based sidewalls or spacers and the silicon or metal based etch layer, wherein the selectively etching the carbon based mask layer undercuts the silicon based sidewalls or spacers, comprising; flowing an oxygen based etch gas into the plasma chamber; forming a plasma from the oxygen based etch gas; and stopping the flow of the oxygen based etch gas selectively etching the silicon or metal based etch layer with respect to the carbon based mask layer and simultaneously removing the silicon based sidewalls; and removing the stack and substrate from the support and the plasma chamber. 2. The method, as recited in claim 1 , wherein the selectively etching the carbon based mask layer selectively etches the carbon based mask layer with respect to the silicon or metal based etch layer. 3. The method, as recited in claim 2 , wherein the carbon based mask layer is a BARC layer. 4. The method, as recited in claim 3 , wherein the silicon or metal based etch layer is over a sublayer, further comprising etching the sublayer after etching the silicon or metal based etch layer. 5. The method, as recited in claim 4 , wherein the silicon or metal based etch layer is a DARC layer. 6. The method, as recited in claim 5 , wherein the silicon based layer is a silicon oxide or silicon nitride based layer. 7. The method, as recited in claim 6 , wherein organic mask is a photoresist mask. 8. The method, as recited in claim 7 , wherein the plasma chamber is an inductively coupled plasma chamber.

Assignees

Inventors

Classifications

  • characterised by the processes involved to create the masks · CPC title

  • characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

  • using an anti-reflective coating · CPC title

  • characterised by their composition, e.g. multilayer masks · CPC title

  • characterised by their composition, e.g. multilayer masks or materials · CPC title

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Frequently asked questions

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What does patent US9711359B2 cover?
A method for etching an etch layer in a stack over a substrate wherein the etch layer is under a mask layer which is under a patterned organic mask is provided. The stack and substrate is placed on a support in the plasma chamber. A silicon based layer is deposited in situ over the stack. The silicon based layer is etched to form silicon based sidewalls or spacers on sides of the patterned orga…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P76/4083. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).