Semiconductor device manufacturing method using a multilayer resist

Patent metadata

Field	Value
Publication number	US-9711344-B2
Application number	US-201615015217-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Feb 24, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

To improve the manufacturing yield of a semiconductor device, there is to provide a method of manufacturing a semiconductor device using a multilayer resist, in which before performing water repelling processing for immersion exposure on a wafer, an anti-reflection film, an underlayer film, and an intermediate film applied to a wafer edge portion are eliminated through rinse processing.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising the following steps of:
(a) preparing a semiconductor wafer comprised of a top surface, a rear surface opposite to the top surface, and a lateral surface between the top surface and the rear surface;
(b) forming a target film on the top surface of the semiconductor wafer;
(c) applying a first insulating layer that is a first mask film on the top surface and the lateral surface of the semiconductor wafer to cover the target film;
(d) eliminating a part of the first insulating layer formed on the lateral surface of the semiconductor wafer, by cleaning the semiconductor wafer;
(e) performing water repelling processing on the first insulating layer, after the step (d);
(f) applying a second insulating layer that is a second mask film on the semiconductor wafer, after the step (e);
(g) transferring a predetermined pattern to the second insulating layer according to photolithography, to form the second mask film;
(h) transferring the pattern of the second mask film to the first insulating layer, to form the first mask film; and
(i) etching the target film, using the first mask film.

2. The method according to claim 1 ,
wherein the first insulating layer is a composite film including at least two layers of an underlayer film and an intermediate layer film.

3. The method according to claim 2 ,
wherein the intermediate layer film includes a silicon component.

4. The method according to claim 1 ,
wherein the first insulating layer is a light absorption film.

5. The method according to claim 1 ,
wherein immersion exposure is used for the photolithography in the step (g).

6. The method according to claim 1 ,
wherein the water repelling processing is HMDS processing according to a gas phase introduction method.

7. The method according to claim 1 ,
between the step (e) and the step (f), further including the following steps of:
(j) applying a third insulating layer that is a third mask film on the semiconductor wafer; and
(k) eliminating a part of the third insulating layer formed on the lateral surface of the semiconductor wafer, by cleaning the semiconductor wafer.

8. The method according to claim 7 ,
wherein the third insulating layer includes a silicon component.

9. A method of manufacturing a semiconductor device comprising the following steps of:
(a) preparing a semiconductor wafer comprised of a top surface, a rear surface opposite to the top surface, and a lateral surface between the top surface and the rear surface;
(b) forming a target film on the top surface of the semiconductor wafer;
(c) applying a first insulating layer on the top surface and the lateral surface of the semiconductor wafer to cover the target film;
(d) eliminating a part of the first insulating layer applied on the lateral surface of the semiconductor wafer by cleaning;
(e) performing water repelling processing on the first insulating layer, after the step (d);
(f) applying a second insulating layer on the semiconductor wafer, after the step (e);
(g) transferring a predetermined pattern to the second insulating layer according to photolithography to form a mask film; and
(h) etching the first insulating layer and the target film using the mask film.

10. The method according to claim 9 ,
wherein the first insulating layer is a light absorption BARC film.

11. The method according to claim 9 ,
wherein immersion exposure is used for the photolithography in the step (g).

12. The method according to claim 9 ,
wherein the water repelling processing is HMDS processing according to a gas phase introduction method.

Assignees

• Renesas Electronics Corp

Inventors

• Suganaga Toshifumi

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P70/54 Primary

  Cleaning of wafer edges · CPC title

• H01L21/0332

  Electricity · mapped topic