Nonvolatile memory device, storage device having the same, operating method thereof

Patent metadata

Field	Value
Publication number	US-9711235-B2
Application number	US-201615295536-A
Country	US
Kind code	B2
Filing date	Oct 17, 2016
Priority date	Oct 23, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A nonvolatile memory device includes a voltage generating circuit configured to generate voltages applied to word lines corresponding to a selected memory block among memory blocks. The voltage generating circuit includes voltage source lines having linear voltages, a first voltage generating unit configured to generate a first voltage and apply the generated first voltage to a first voltage source line among the voltage source lines, a second voltage generating unit configured to generate a second voltage and apply the generated second voltage to a second voltage source line among the voltage source lines, and a linear voltage generator having a resistor string connected between the first voltage source line and the second voltage source line. At least one of the voltage source lines has a voltage distributed between the first voltage and the second voltage.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a plurality of memory blocks having a plurality of strings which are perpendicular to a substrate and are connected to one bit line, wherein each of the cell strings comprises a plurality of memory cells corresponding to word lines, respectively; and
a voltage generating circuit configured to generate voltages that are applied to word lines corresponding to a memory block selected from the memory blocks, wherein:
the voltage generating circuit comprises:
voltage source lines having the voltages corresponding to the word lines;
a first voltage generating unit configured to generate a first voltage and apply the first voltage to a first voltage source line of the voltage source lines;
a second voltage generating unit configured to generate a second voltage and apply the second voltage to a second voltage source line of the voltage source lines; and
a resistor string connected between the first voltage source line and the second voltage source line, and

at least one of the voltage source lines has a voltage between the first voltage and the second voltage divided using the resistor string.

2. The nonvolatile memory device of claim 1 , wherein each of the first and second voltage generating units comprises:
a variable resistor string connected between a power supply terminal and a ground terminal; and
a voltage follower configured to output a division voltage between a source voltage applied to the power supply terminal and a ground voltage of the ground terminal as the first voltage or the second voltage.

3. The nonvolatile memory device of claim 2 , further comprising a source voltage generator configured to generate the source voltage.

4. The nonvolatile memory device of claim 1 , wherein waveforms of the voltages linearly increase from the first voltage to the second voltage, linearly decrease from the first voltage to the second voltage, are maintained with the first voltage, or are maintained with the second voltage.

5. The nonvolatile memory device of claim 1 , further comprising at least one third voltage generating unit configured to generate a third voltage and apply the third voltage to a third source line of the voltage source lines.

6. The nonvolatile memory device of claim 5 , wherein the at least one third voltage generating unit further comprises a switch transistor configured to determine whether to apply the third voltage to the third voltage source line.

7. The nonvolatile memory device of claim 5 , wherein the at least one third voltage generating unit further comprises:
a first switch transistor configured to determine whether to apply the third voltage to the third voltage source line; and
at least one second switch transistor configured to determine whether to apply the third voltage to a fourth voltage source line of the voltage source lines.

8. The nonvolatile memory device of claim 1 , wherein the voltage generating circuit further comprises pass transistors configured to connect the word lines to the voltage source lines.

9. The nonvolatile memory device of claim 8 , wherein the voltage generating circuit further comprises a high-voltage level shifter configured to convert a voltage level of an enable signal and apply the converted enable signal to gates of the pass transistors.

10. The nonvolatile memory device of claim 1 , wherein:
the voltage generating circuit further comprises:
an erase voltage generator configured to generate an erase voltage that is applied to a well of the selected memory block; and
a word line erase voltage generator configured to generate word line erase voltages that are applied to word lines of the selected memory block, and

the word line erase voltage generator comprises a linear voltage generator.

11. The nonvolatile memory device of claim 1 , wherein:
the voltage generating circuit further comprises:
a selection word line voltage generator configured to generate a word line voltage that is applied to a word line of the selected memory block; and
a non-selection word line voltage generator configured to generate non-selection word line voltages that are applied to unselected word lines of the selected memory block, and

the non-selection word line voltage generator comprises a linear voltage generator.

12. The nonvolatile memory device of claim 1 , wherein:
the word lines are divided into a plurality of zones,
the voltage generating circuit further comprises a plurality of zone-voltage generators corresponding to the plurality of zones, each of the zone-voltage generators configured to generate word line voltages that are applied to word lines of a corresponding zone, and
at least one of the zone-voltage generators comprises a linear voltage generator.

13. A method of operating a nonvolatile memory device having a plurality of strings perpendicular to a substrate, the method comprising:
generating a source voltage;
generating linear voltages by dividing a voltage between the source voltage and a ground voltage using a resistor string; and
applying the linear voltages to word lines, wherein
the linear voltages are word line voltages which linearly increase or decrease at all or a portion of adjacent word lines during a program, a read, or an erase operation.

14. The method of claim 13 , further comprising setting waveforms of linear voltages based on positions of word lines of a selected memory block.

15. The method of claim 13 , further comprising:
generating an erase voltage during an erase operation; and
applying the erase voltage to a well of a selected memory block.

16. The method of claim 15 , wherein the applying of the linear voltages comprises:
electrically isolating the word lines from an address decoder during the erase operation; and
connecting the word lines to voltage source lines having the linear voltages.

17. A nonvolatile memory device comprising:
word lines; and
an erase voltage generator configured to generate word line erase voltages that are applied to the word lines during an erase operation, wherein:
the erase voltage generator comprises:
pass transistors configured to electrically connect the word lines to voltage source lines;
a resistor string configured to electrically connect the voltage source lines;
a plurality of voltage generating units configured to generate voltages corresponding to a portion of the voltage source lines and apply the generated voltages to the corresponding voltage source lines; and
a high-voltage level shifter configured to receive an enable signal during the erase operation and convert a level of the enable signal, and

the pass transistors are turned on in response to the level-converted enable signal.

18. The nonvolatile memory device of claim 17 , further comprising a switch transistor configured to connect at least one of the voltage generating units to a corresponding voltage source line through a switching operation.

19. The nonvolatile memory device of claim 17 , further comprising switch transistors configured to connect at least two of the voltage source lines to at least one of the voltage generating units through a switching operation.

20. The nonvolatile memory device of claim 17 , further comprising a three dimensional (3D) memory array.

Assignees

• Gangasani Venkataramana
• Lee Jin-Yub
• Seo Sungwhan
• Kim Won-Tae
• Lee Dojeon
• Lee Yohan
• Samsung Electronics Co Ltd

Inventors

• Gangasani Venkataramana
• Lee Jin-Yub
• Seo Sungwhan
• Kim Won-Tae
• Lee Dojeon
• Lee Yohan

Classifications

• G11C16/0466 Primary

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title