Delay-compensated error indication signal

Patent metadata

Field	Value
Publication number	US-9710323-B2
Application number	US-201213997850-A
Country	US
Kind code	B2
Filing date	Mar 31, 2012
Priority date	Mar 31, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

First claim

What is claimed is:

1. A memory module comprising:
multiple dynamic random access memory (DRAM) devices to store data;
an address and command (ADD/CMD) signal line coupled to the DRAM devices and capable to couple to a memory controller, wherein the ADD/CMD signal line is capable to be driven with a command signal from the memory controller when coupled; and
an error alert signal line coupled to the DRAM devices and capable to couple to the memory controller, one or more of the DRAM devices capable to drive an error alert signal on the error alert signal line in response to an error detection,
wherein a DRAM device to be closest to the memory controller along a physical routing of the ADD/CMD signal line is to be farthest from the memory controller along a physical routing of the error alert signal line, and a DRAM device to be farthest from the memory controller along the physical routing of the ADD/CMD signal line is to be closest to the memory controller along the physical routing of the error alert signal line.

2. The memory module of claim 1 , wherein one or more of the DRAM devices capable to drive the error alert signal line in response to detection of a parity error in a command/address signal.

3. The memory module of claim 1 , wherein the ADD/CMD signal line to be physically routed from a DRAM device of lowest address to a DRAM device of highest address, and the error alert signal line to be physically routed from the DRAM device of highest address to the DRAM device of the lowest address.

4. The memory module of claim 1 , wherein the DRAM devices comprise DRAM devices of a SO-DIMM.

5. The memory module of claim 1 , wherein the DRAM devices comprise DRAM devices of a UDIMM.

6. The memory module of claim 1 , wherein one or more of the DRAM devices capable to drive the error alert signal line in response to detection of a cyclic redundancy check (CRC) error in the C/A signal.

7. The memory module of claim 1 , wherein the ADD/CMD signal line comprises a signal line of a fly-by-topology command/address (C/A) bus to couple to the DRAMs one at a time in sequence.

8. The memory module of claim 1 , wherein the ADD/CMD signal line comprises a trace on a dual inline memory module (DIMM) to carry the command signal to the DRAM devices.

9. A memory subsystem comprising:
a memory controller including
logic to drive a command/address (C/A) signal on an address and command (ADD/CMD) signal line; and
logic to receive an error alert signal over an error alert signal line in response to an error detection for the C/A signal; and

a dual in-line memory module (DIMM) coupled with the memory controller, the DIMM including
multiple synchronous dynamic random access memory (SDRAM) devices coupled to the ADD/CMD signal line and the error alert signal line;

wherein an SDRAM device to be closest to the memory controller along a physical routing of the ADD/CMD signal line is to be farthest away from the memory controller along a physical routing of the error alert signal line, and an SDRAM device to be farthest from the memory controller along the physical routing of the ADD/CMD signal line is to be closest to the memory controller along the physical routing of the error alert signal line.

10. The memory subsystem of claim 9 , wherein one or more of the SDRAM devices capable to drive the error alert signal line in response to detection of a parity error in the C/A signal.

11. The memory subsystem of claim 9 , wherein the ADD/CMD signal line to be physically routed from a SDRAM device of lowest address to a SDRAM device of highest address, and the error alert signal line to be physically routed from the SDRAM device of highest address to the SDRAM device of the lowest address.

12. The memory subsystem of claim 9 , wherein the memory controller capable to store a recovery history comprising a number of entries based on a worst case timing of the error alert signal.

13. The memory subsystem of claim 9 , wherein the DIMM comprises a SO-DIMM.

14. The memory subsystem of claim 9 , wherein the DIMM comprises a UDIMM.

15. The memory subsystem of claim 9 , wherein one or more of the SDRAM devices capable to drive the error alert signal line in response to detection of a cyclic redundancy check (CRC) error in the C/A signal.

16. The memory subsystem of claim 9 , wherein the ADD/CMD signal line comprises a signal line of a fly-by-topology C/A bus to couple to the SDRAMs one at a time in sequence.

17. The memory subsystem of claim 9 , wherein the ADD/CMD signal line comprises a trace on a dual inline memory module (DIMM) to carry the C/A signal to the SDRAM devices.

18. An electronic device comprising:
a memory subsystem having comprising
a memory controller including logic to drive a command/address (C/A) signal on an address and command (ADD/CMD) signal line, and logic to receive an error alert signal over an error alert signal line in response to an error detection for the C/A signal, and
a dual in-line memory module (DIMM) coupled with the memory controller, the DIMM including multiple synchronous dynamic random access memory (SDRAM) devices coupled to the ADD/CMD signal line and the error alert signal line,
wherein an SDRAM device to be closest to the memory controller along a physical routing of the ADD/CMD signal line is to be farthest away from the memory controller along a physical routing of the error alert signal line, and an SDRAM device to be farthest from the memory controller along the physical routing of the ADD/CMD signal line is to be closest to the memory controller along the physical routing of the error alert signal line; and

a multicore processor coupled to the memory subsystem to access the memory subsystem during execution of the processor.

19. The device of claim 18 , wherein one or more of the SDRAM devices capable to drive the error alert signal line in response to detection of a parity error in the C/A signal.

20. The device of claim 18 , wherein the SDRAM devices capable to drive the error alert signal line in response to detection of a cyclic redundancy check (CRC) error in the C/A signal.

21. The device of claim 18 , wherein the ADD/CMD signal line to be physically routed from a SDRAM device of lowest address to a SDRAM device of highest address, and the error alert signal line to be physically routed from the SDRAM device of highest address to the SDRAM device of the lowest address.

22. The device of claim 18 , wherein the memory controller capable to store a recovery history comprising a number of entries based on a worst case timing of the error alert signal.

23. The device of claim 18 , wherein the DIMM comprises a first DIMM, and wherein the memory subsystem further comprises a second DIMM coupled with the memory controller, the second DIMM including multiple SDRAM devices coupled to the ADD/CMD signal line and the error alert signal line, wherein the C/A signal to be physically routed on the ADD/CMD signal line in a first direction, and the error alert signal to be physically routed on the error alert signal line in a second direction opposite to the first direction at the second DIMM.

24. The device of claim 18 , wherein the DIMM comprises a SO-DIMM.

25. The device of claim 18 , wherein the DIMM comprises a UDIMM.

26. The device of claim 18 , wherein the ADD/CMD signal line comprises a signal line of a fly-by-topology C/A bus to couple to the SDRAMs one at a time in sequence.

Assignees

• Bains Kuljit Singh
• Vergis George
• Intel Corp

Inventors

• Bains Kuljit Singh
• Vergis George

Classifications

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/108

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title