Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate

Patent metadata

Field	Value
Publication number	US-9709740-B2
Application number	US-201213487573-A
Country	US
Kind code	B2
Filing date	Jun 4, 2012
Priority date	Jun 4, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide is optically decoupled from a support substrate by a shallow trench isolation region.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A method of forming an integrated structure, the method comprising the acts of:
providing a first substrate having an upper surface;
after providing the first substrate, removing material from the upper surface only partially through a thickness of the first substrate to form a shallow trench isolation region in the upper surface, the shallow trench isolation region extending only partially through a thickness of the first substrate;
after forming the shallow trench isolation region, depositing a dielectric material having a first index of refraction over the upper surface and in the shallow trench isolation region;
planarizing the dielectric material such that the dielectric material fills the shallow trench isolation region;
forming a photonics area on a second substrate;
bonding the first and second substrates together such that the upper surface of the first substrate faces the second substrate and the shallow trench isolation region is aligned with the photonics area; and
forming a waveguide within the photonics area, wherein the waveguide comprises a core formed of a material having a second index of refraction greater than the first index of refraction.

2. A method as in claim 1 , wherein the first and second substrates each comprise a silicon substrate, the photonics area being a silicon photonics area.

3. A method of claim 2 , further comprising forming the waveguide within the silicon photonics area of the bonded substrates, the waveguide including a waveguide core and cladding, with the waveguide core being aligned with the shallow trench isolation region of the bonded substrates.

4. A method as in claim 3 , wherein the waveguide is formed after the first and second substrates are bonded together.

5. A method as in claim 3 , further comprising, prior to said bonding: forming a BOX as part of said second substrate, which is beneath the waveguide core of the bonded substrates, wherein the combined thickness of the BOX and shallow trench isolation region is at least 1 um, the bonded substrates forming a silicon-on-insulator structure.

6. A method as in claim 5 , wherein the thickness of the BOX is less than or equal to 200 nm.

7. A method as in claim 5 , wherein the thickness of the shallow trench isolation region is in the range of about 800 nm to about 1200 nm.

8. A method as in claim 3 , further comprising forming a cladding region to surround the waveguide core, the cladding region being formed at least in part by a first dielectric on the second substrate located below the waveguide.

9. A method as in claim 8 , wherein the waveguide core is formed of silicon and the first dielectric comprises an oxide.

10. A method as in claim 9 , wherein the first dielectric comprises silicon dioxide.

11. A method as in claim 8 , wherein the cladding region further comprises a second dielectric on the sides of the waveguide.

12. A method as in claim 9 , wherein said first and second dielectrics comprise silicon dioxide.

13. A method as in claim 2 , wherein the bonding further comprises forming an amorphous silicon on at least one of the first and second substrates and pressing the substrates together such that the amorphous silicon functions as a bonding material to bond the first substrate to the second substrate.

14. A method as in claim 2 , wherein the second substrate further comprises an insulator, and the bonding of the first and second substrates forms a silicon-on-insulator structure having a buried insulator.

15. A method as in claim 2 , wherein the second substrate further comprises dielectric material adjacent the silicon, the method further comprising thinning the second substrate silicon before the waveguide is formed.

16. A method as in claim 15 , wherein the second substrate silicon is thinned by implanting a dopant to form a cleave line and then cleaving along the cleave line to remove a portion of the silicon.

17. A method as in claim 16 , further comprising recycling the removed portion of the second substrate silicon for use as a substrate in another integrated structure.

18. A method as in claim 2 , comprising thinning the first substrate from a side opposite a side containing the shallow trench isolation region.

19. A method as in claim 18 , wherein the thinning of the first substrate comprises implanting a dopant into the silicon of the first substrate to form a cleave line and then cleaving the silicon of the first substrate along the cleave line to remove a portion of the silicon.

20. A method as in claim 19 , further comprising recycling the removed portion of the silicon of the first substrate for use as a substrate in another integrated structure.

21. A method as in claim 1 , wherein the first and second substrates comprise a semiconductor material with the photonics area being formed of the semiconductor material of the second substrate, said method further comprising forming the waveguide core using the semiconductor material of the second substrate.

22. A method as in claim 21 , wherein the semiconductor material comprises silicon.

23. A method as in claim 1 , further comprising forming a circuit element area on the second substrate.

24. A method of forming an integrated structure, the method comprising:
providing a first substrate having an upper surface;
etching through only a portion of a thickness of the first substrate to form a shallow trench isolation region in the upper surface such that the shallow trench isolation region extends through only a portion of the thickness of the first substrate;
after forming the shallow trench isolation region, depositing a dielectric material having a first index of refraction into the shallow trench isolation region;
planarizing the dielectric material such that the dielectric material fills the shallow trench isolation region;
forming a photonics area on a second substrate;
bonding the first and second substrates together such that the upper surface of the first substrate faces the second substrate and the shallow trench isolation region is aligned with the photonics area; and
forming a waveguide within the photonics area aligned with the shallow trench isolation region, wherein the shallow trench isolation region is configured to reduce optical coupling between the waveguide and the first substrate.

25. The method of claim 24 , wherein the waveguide comprises a waveguide core formed of a material having a second index of refraction greater than the first index of refraction.

26. The method of claim 24 , wherein the first and second substrates each comprise a silicon substrate, the photonics area being a silicon photonics area.

27. The method of claim 26 , further comprising forming the waveguide within the silicon photonics area such that the waveguide core is aligned with the shallow trench isolation region.

28. The method of claim 24 , further comprising forming a BOX as part of said second substrate beneath the photonics area, wherein the combined thickness of the BOX and shallow trench isolation region is at least 1 μm.

29. The method of claim 24 , further comprising forming a cladding region to surround the waveguide core, the cladding region being formed at least in part by a first dielectric on the second substrate located below the waveguide.

Assignees

• Meade Roy
• Micron Technology Inc

Inventors

• Meade Roy

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title