Flexible substrate embedded with wires and method for fabricating the same

US9707706B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9707706-B2
Application numberUS-201514627913-A
CountryUS
Kind codeB2
Filing dateFeb 20, 2015
Priority dateFeb 25, 2014
Publication dateJul 18, 2017
Grant dateJul 18, 2017

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A flexible substrate embedded with wires includes a flexible substrate constituted by a polymer material, and a continuous wire pattern containing a plurality of pores embedded in the flexible substrate, wherein the polymer material fills the pores. A method for fabricating a flexible substrate embedded with wires providing a carrier; forming a continuous wire pattern on the carrier, the continuous wire pattern containing a plurality of pores; covering a polymer material over the continuous wire pattern and the carrier and to fill into the pores; and separating the polymer material and the carrier to form a flexible substrate embedded with the continuous wire pattern” where the only change is the addition of wires.

First claim

Opening claim text (preview).

What is claimed is: 1. A flexible substrate embedded with wires, comprising: a flexible substrate constituted by a polymer material; and a continuous wire pattern containing a plurality of pores embedded in the flexible substrate, wherein the polymer material fills the pores. 2. The flexible substrate embedded with wires as claimed in claim 1 , wherein the polymer material comprises polyimide (PI) or polyvinylidene fluoride (PVDF). 3. The flexible substrate embedded with wires as claimed in claim 1 , wherein the wire pattern comprises silver, copper, nickel or an alloy thereof. 4. The flexible substrate embedded with wires as claimed in claim 1 , wherein the wire pattern has a resistivity ranging from 1.6×10 −6 Ω·cm to 10×10 −6 Ω·cm. 5. The flexible substrate embedded with wires as claimed in claim 1 , wherein the pore has a size ranging from 10 nm to 100 μm. 6. The flexible substrate embedded with wires as claimed in claim 1 , wherein the continuous wire pattern is embedded in an area inside the flexible substrate. 7. The flexible substrate embedded with wires as claimed in claim 1 , wherein the continuous wire pattern is embedded in an area near a surface of the flexible substrate. 8. A method for fabricating a flexible substrate embedded with wires, comprising: providing a carrier; forming a continuous wire pattern on the carrier, wherein the continuous wire pattern contains a plurality of pores; covering a polymer material over the continuous wire pattern and the carrier and to fill into the pores; and separating the polymer material and the carrier to form a flexible substrate embedded with the continuous wire pattern. 9. The method for fabricating a flexible substrate embedded with wires as claimed in claim 8 , wherein the carrier comprises glass or metal. 10. The method for fabricating a flexible substrate embedded with wires as claimed in claim 8 , further comprising performing a surface treatment process on the flexible substrate embedded with the continuous wire pattern. 11. The method for fabricating a flexible substrate embedded with wires as claimed in claim 8 , wherein the step of forming a continuous wire pattern on the carrier comprises: providing a metal glue with a solid content ranging from 80% to 85%; forming a continuous pattern of the metal glue on the carrier; and performing a sintering process on the carrier, wherein the sintering process has a sintering temperature ranging from 300° C. to 350° C. and a sintering time ranging from 30 min to 40 min. 12. The method for fabricating a flexible substrate embedded with wires as claimed in claim 8 , wherein the step of covering a polymer material over the continuous wire pattern and the carrier comprises: providing a polyvinylidene fluoride (PVDF) with a solid content ranging from 5% to 30%; forming a polyvinylidene fluoride (PVDF) layer on the continuous wire pattern and the carrier; and performing a baking process on the carrier, wherein the baking process has a baking temperature ranging from 50° C. to 180° C. and a baking time ranging from 10 min to 30 min. 13. The method for fabricating a flexible substrate embedded with wires as claimed in claim 8 , wherein the step of covering a polymer material over the continuous wire pattern and the carrier comprises: providing a polyimide (PI) with a solid content ranging from 5% to 40%; forming a polyimide (PI) layer on the continuous wire pattern and the carrier; and performing a baking process on the carrier, wherein the baking process has a baking temperature ranging from 50° C. to 210° C. and a baking time ranging from 30 min to 60 min.

Assignees

Inventors

Classifications

  • PVDF, i.e. polyvinylidene fluoride · CPC title

  • Anchoring, i.e. one structure gripping into another · CPC title

  • Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity · CPC title

  • H05K3/207Primary

    using a prefabricated paste pattern, ink pattern or powder pattern · CPC title

  • PI, i.e. polyimides or derivatives thereof · CPC title

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Frequently asked questions

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What does patent US9707706B2 cover?
A flexible substrate embedded with wires includes a flexible substrate constituted by a polymer material, and a continuous wire pattern containing a plurality of pores embedded in the flexible substrate, wherein the polymer material fills the pores. A method for fabricating a flexible substrate embedded with wires providing a carrier; forming a continuous wire pattern on the carrier, the contin…
Who is the assignee on this patent?
Ind Tech Res Inst
What technology area does this patent fall under?
Primary CPC classification H05K3/207. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 18 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).