Printed circuit board and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9706652-B2
Application number	US-201113997596-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 24, 2010
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A printed circuit board according the present embodiment includes an insulating layer; at least one circuit pattern or pad formed on the insulating layer; a solder resist having an opening section exposing the upper surface of the pad and formed on the insulating layer and a bump formed on the pad exposed through the opening section of the solder resist and having a lower area narrower than the upper area.

First claim

What is claimed is:

1. A printed circuit board, comprising:
an insulating layer;
at least one circuit pattern or pad formed on the insulating layer;
a solder resist having an opening section exposing an upper surface of the at least one circuit pattern or pad and formed on the insulating layer;
a seed layer formed at a side surface of the solder resist exposing the upper surface of the at least one circuit pattern or pad, and protruded over a surface of the solder resist; and
a bump formed on the pad exposed through the opening section of the solder resist and seed layer, and protruded over the surface of the solder resist;
wherein the seed layer is disposed between the side surface of the solder resist and a side surface of the bump,
wherein the seed layer has an upper surface and a lower surface opposite to the upper surface,
wherein an area of the upper surface of the seed layer is the same as that of the lower surface of the seed layer,
wherein a height of the seed layer is the same as a height of the bump,
wherein the upper surface of the protruded seed layer lies in a same plane as an upper surface of the protruded bump,
wherein the bump comprises:
a first bump on the at least one circuit pattern or pad exposed through the opening section of the solder resist and formed with an alloy containing copper; and
a second bump on the first bump, formed with an alloy containing tin and protruded over an upper surface of the solder resist, wherein the upper surface of the protruded seed layer lies in a same plane as an upper surface of the second bump,

wherein an upper surface of the first bump is higher than the upper surface of the solder resist,
wherein the seed layer is contacted with side surfaces of the first bump and the second bump,
wherein an area of an upper surface of the first bump is the same as that of a lower surface of the first bump,
wherein an area of an upper surface of the second bump is the same as that of a lower surface of the second bump, and
wherein the area of the upper surface of the first bump is the same as that of the upper surface of the second bump.

2. A method for manufacturing a printed circuit board, comprising:
forming a pad on an insulating board;
applying a solder resist having an opening section exposing an upper surface of the pad to the insulating board;
forming a mask, having a window opening the opening section, on the opening section;
forming a plating layer surrounding an upper surface and a side surface of the mask, and exposing the upper surface of the pad;
forming a bump embedding the opening section of the solder resist and the window of the mask on the upper surface of the exposed pad; and
removing the mask and a portion of the plating layer;
wherein, after the portion of the plating layer is removed, the plating layer has an upper surface and a lower surface opposite to the upper surface;
wherein an area of the upper surface of the plating layer is the same as that of the lower surface of the plating layer;
wherein upper surfaces of the plating layer and the bump are protruded over a surface of the solder resist;
wherein a height of the plating layer is the same as a height of the bump;
wherein the upper surface of the protruded plating layer lies in a same plane as the upper surface of the protruded bump,
wherein the forming of the bump comprises:
plating an alloy including copper using the plating layer as a seed layer and forming a first bump embedding a portion of the opening section of the solder resist and a portion of the window of the mask; and
plating an alloy containing tin on the first bump and forming a second bump embedding the opening section of the solder resist and the window of the mask,

wherein an upper surface of the seed layer lies in a same plane as an upper surface of the second bump,
wherein an upper surface of the first bump is higher than an upper surface of the solder resist,
wherein the seed layer is contacted with side surfaces of the first bump and the second bump,
wherein an area of an upper surface of the first bump is the same as that of a lower surface of the first bump,
wherein an area of an upper surface of the second bump is the same as that of a lower surface of the second bump, and
wherein the area of the upper surface of the first bump is the same as that of the upper surface of the second bump.

3. The method of claim 2 , wherein the forming of the mask includes stacking a dry film opening the opening section on the solder resist.

4. The method of claim 2 , wherein the forming of the mask includes forming the mask having the window of the same area as the opening section of the solder resist.

5. The method of claim 2 , wherein the applying of the solder resist includes:
applying the solder resist embedding the pad to the insulating board; and
performing a laser machining on the applied solder resist and forming the opening section exposing the upper surface of the pad.

6. The method of claim 2 , wherein the forming of the mask includes:
stacking the mask embedding the pad on the solder resist; and
forming the window exposing the pad by performing a laser machining on the stacked mask.

7. The method of claim 2 , wherein the opening section of the solder resist and the window of the mask are simultaneously formed by a laser machining.

8. The method of claim 2 , wherein the mask includes a dry film.

9. The method of claim 2 , further comprising,
forming a separate protective layer on the solder resist before forming the mask,
wherein the mask is formed on the separate protective layer, and
wherein the separate protective layer is formed of a metal different from the first and second bumps.

Assignees

• Ryu Sung Wuk
• Shim Seong Bo
• Shin Seung Yul
• Lg Innotek Co Ltd

Inventors

• Ryu Sung Wuk
• Shim Seong Bo
• Shin Seung Yul

Classifications

• H05K2203/054

  Continuous temporary metal layer over resist, e.g. for selective electroplating · CPC title

• H05K3/3473

  Plating of solder · CPC title

• H05K2203/0577

  Double layer of resist having the same pattern · CPC title

• H05K2201/0367

  Metallic bump or raised conductor not used as solder bump · CPC title

• H05K3/28

  Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)} · CPC title