Parallel low-density parity check (LDPC) accumulation

Patent metadata

Field	Value
Publication number	US-9705532-B2
Application number	US-201414207459-A
Country	US
Kind code	B2
Filing date	Mar 12, 2014
Priority date	Mar 15, 2013
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Systems and methods for parallel accumulation of information bits as part of the generation of low-density parity-check codes are provided. Consecutive information bits can be accumulated through vector operations where the parity addresses used for accumulation can be made contiguous through a virtual to private parity address map. The method for accumulating a set of parity bits for an encoding operation may comprise the steps of performing an exclusive or (XOR) between a multi-bit vector containing information bits and a multi-bit vector of parity bits in an encoder, and storing results of the XOR as a set of parity bits. An encoder for accumulating the set of parity bits is also provided.

First claim

I claim:

1. A method for accumulating a set of parity bits for an encoding operation, comprising the steps of:
establishing, in an encoder, a virtual address for each of a set of pre-defined addresses of parity bits in memory, wherein the pre-defined addresses are non-consecutive addresses in random access memory (RAM);
generating, in the encoder, a multi-bit vector of parity bits by reading parity bits from consecutive ones of the virtual addresses;
performing an exclusive or (XOR) operation between a multi-bit vector containing information bits and the multi-bit vector of parity bits in the encoder; and
storing results of the XOR operation as a set of parity bits.

2. The method according to claim 1 , wherein the storing step includes writing the results of the XOR operation to the consecutive addresses of the virtual addresses.

3. The method according to claim 1 , further comprising the step of mapping values of the parity bits stored in the virtual addresses to the pre-defined addresses after said storing step.

4. The method according to claim 1 , further comprising the step of mapping each of the pre-defined addresses to a corresponding one of the virtual addresses and initializing the parity bits with a pre-determined value before said generating step.

5. The method according to claim 1 , wherein the encoding operation is a low-density parity check (LDPC) encoding operation.

6. The method according to claim 1 , wherein each of the multi-bit vector containing information bits and the multi-bit vector of parity bits includes up to 360 binary bits.

7. The method according to claim 1 , wherein the XOR operation is accomplished simultaneously in parallel operations for all bits in the multi-bit vectors.

8. A forward error correction (FEC) device comprising an encoder, the encoder comprising at least one processor communicatively coupled to a memory device, the encoder configured to:
perform an exclusive or (XOR) operation between a multi-bit vector containing information bits and a multi-bit vector of parity bits;
store results of the XOR operation as a set of parity bits in the memory device;
establish a virtual address for each of a set of pre-defined addresses of parity bits in the memory device, wherein the pre-defined addresses are non-consecutive addresses in random access memory (RAM); and
generate the multi-bit vector of parity bits by reading parity bits from consecutive ones of the virtual addresses.

9. The FEC device according to claim 8 , wherein the encoder is configured to perform the XOR operation simultaneously in parallel operations for all bits in the multi-bit vectors.

10. The FEC device according to claim 8 , wherein the encoder is a low-density parity check (LDPC) encoder.

11. The FEC device according to claim 8 , wherein each of the multi-bit vector containing information bits and the multi-bit vector of parity bits includes up to 360 binary bits.

12. The FEC device according to claim 8 , wherein the encoder is configured to store the results of the XOR operation by writing the results of the XOR operation to the consecutive addresses of the virtual addresses.

13. The FEC device according to claim 8 , wherein the encoder is configured to map values of the parity bits stored in the virtual addresses and resulting from the XOR operation to the pre-defined addresses.

14. The FEC device according to claim 8 , wherein the encoder is configured to map each of the pre-defined addresses to a corresponding one of the virtual addresses and initialize the parity bits with a pre-determined value before performing the XOR operation.

Assignees

• Arris Group Inc
• Arris Entpr Llc

Inventors

• Kharkunou Yury

Classifications

• H03M13/611

  Specific encoding aspects, e.g. encoding by means of decoding · CPC title

• H03M13/6561 Primary

  Parallelized implementations · CPC title

• H03M13/6505

  Memory efficient implementations · CPC title

• H03M13/1165

  QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2] · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title