Error correction processing circuit and error correction processing method

Patent metadata

Field	Value
Publication number	US-9166739-B2
Application number	US-201213488741-A
Country	US
Kind code	B2
Filing date	Jun 5, 2012
Priority date	Jun 24, 2011
Publication date	Oct 20, 2015
Grant date	Oct 20, 2015

Abstract

An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.

First claim

What is claimed is:

1. An error correction processing circuit, comprising:
a division circuit that divides input data into a plurality of pieces of a predetermined data length;
a serial conversion circuit that converts the plurality of pieces of data divided by the division circuit into a plurality of pieces of serial data;
a plurality of encoders that are provided in parallel, and that perform encoding for the plurality of pieces of serial data converted by the serial conversion circuit, respectively;
a parallel conversion circuit that converts the plurality of pieces of data for which the encoding has been performed by the plurality of encoders, into a plurality of pieces of parallel data such that each of the pieces of parallel data corresponds to a bus width in a state before the serial conversion performed by the serial conversion circuit;
a multiplexing circuit that multiplexes the plurality of pieces of parallel data provided in the conversion performed by the parallel conversion circuit;
an output circuit that outputs the data multiplexed by the multiplexing circuit; and
a control circuit configured to receive frame pulses that indicate beginnings of frames of the input data inputted into the division circuit and to control writing and reading data into/from the division circuit and writing and reading data into/from the multiplexing circuit based on the frame pulses.

2. The error correction processing circuit according to claim 1 , further comprising:
an alignment circuit that aligns boundaries among the plurality of pieces of data, wherein
the plurality of encoders perform the encoding for the plurality of pieces of data having the boundaries aligned by the alignment circuit, respectively.

3. The error correction processing circuit according to claim 2 , further comprising:
a plurality of memories into which the plurality of pieces of data having the boundaries aligned by the alignment circuit are written, respectively, wherein
the plurality of encoders perform the encoding for the plurality of pieces of data read from the plurality of memories, respectively.

4. The error correction processing circuit according to claim 2 , further comprising:
a plurality of memories into which the plurality of pieces of data divided by the division circuit are written, respectively, wherein
the alignment circuit aligns the boundaries among the plurality of pieces of data read from the plurality of memories.

5. The error correction processing circuit according to claim 2 , further comprising:
a conversion circuit that converts the plurality of pieces of data for which the encoding has been performed by the plurality of encoders, into sequences in a state before the alignment performed by the alignment circuit, wherein
the multiplexing circuit multiplexes the plurality of pieces of data in the sequences converted by the conversion circuit.

6. An error correction processing method, comprising:
dividing, by a division circuit, input data into a plurality of pieces of a predetermined data length;
converting the plurality of pieces of data into a plurality of pieces of serial data, encoding the plurality of pieces of serial data converted by the converting, respectively, by a plurality of encoders provided in parallel;
converting the plurality of pieces of data for which the encoding has been performed by the plurality of encoders, into a plurality of pieces of parallel data such that each of the pieces of parallel data corresponds to a bus width in a state before the serial conversion;
multiplexing, by a multiplexing circuit, the plurality of pieces of parallel data provided in the conversion performed by the parallel conversion;
outputting the multiplexed data;
receiving frame pulses that indicate beginnings of frames of the input data inputted into the division circuit and controlling writing and reading data into/from the division circuit and writing and reading data into/from the multiplexing circuit based on the frame pulses.

Assignees

• Sakai Toshiharu
• Azumi Ryoji
• Nishisaka Kiyomasa
• Hirata Daisuke
• Kitajima Hiroyuki
• Fujitsu Ltd

Inventors

• Sakai Toshiharu
• Azumi Ryoji
• Nishisaka Kiyomasa
• Hirata Daisuke
• Kitajima Hiroyuki

Classifications

• H04L1/0052 Primary

  Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title

• H03M13/6561

  Parallelized implementations · CPC title