On-chip impedance network with digital coarse and analog fine tuning

Patent metadata

Field	Value
Publication number	US-9705497-B2
Application number	US-201514829511-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	May 23, 2012
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

First claim

The invention claimed is:

1. A method of self-calibrating a configurable resistance on an integrated circuit capable of being coupled to a reference resistor, the method comprising:
(A) tuning a digital resistor network to configure a digital portion of the configurable resistance;
(B) tuning an analog resistor network to configure an analog portion of the configurable resistance;
wherein the configurable resistance comprises the digital resistor network and the analog resistor network coupled in parallel,
wherein the configurable resistance is capable of being coupled in series with the reference resistor to form a voltage divider with an output,
wherein the digital resistor network comprises a plurality of selectable resistive branches in parallel and a plurality of digital control signals, each branch being coupled to one of the digital control signals and selected according to the state of that digital control signal, and
wherein the tuned resistance of the digital resistor network is determined by the combined state of the digital control signals; and
wherein step (A) comprises the sub-steps of:
(A1) varying the number of selected resistive branches in the digital resistor network;
(A2) comparing the voltage at the output of the voltage divider to a reference voltage when the number of selected resistive branches is varied;
(A3) determining from the voltage comparisons a first combined state of the digital control signals required to produce the lowest value of voltage at the output of the voltage divider that is higher than the reference voltage;
(A4) determining from the voltage comparisons a second combined state of the digital control signals required to produce the highest value of voltage at the output of the voltage divider that is lower than the reference voltage;
(A5) selecting the one of the first combined state of digital control signals and the second combined state of digital control signals that determines the larger tuned resistance of the digital resistor network; and
(A6) storing the selected one of the first combined state of the digital control signals and the second combined state of the digital control signals.

2. The method of claim 1 :
wherein the analog resistor network comprises a variable resistive branch coupled to an analog control signal;
wherein the tuned resistance of the analog resistor network is determined by the value of the analog signal; and
wherein an amplifier has an output coupled to the analog signal, a first input coupled to the reference voltage, and a second input coupled to the output of the voltage divider.

3. The method of claim 2 wherein step (B) comprises the sub-steps of:
(B1) comparing the reference voltage to the voltage at the output of the resistor divider; and
(B2) controlling the value of the analog signal to tune the resistance of the analog resistor network such that the reference voltage and the voltage at the output of the voltage divider are substantially equal.

4. The method of claim 3 further comprising the steps of:
(C) placing the integrated circuit into a low power mode wherein the configurable resistance is placed into a high impedance state;
(D) exiting the integrated circuit from the low power mode wherein the configurable resistance is placed into a conductive state;
(E) retrieving the stored combined state of the digital control signals; and
(F) applying the stored combined state of the digital control signals to the digital resistive network.

5. The method of claim 4 wherein the reference resistor is external to the integrated circuit.

6. The method of claim 3 wherein the reference resistor is external to the integrated circuit.

7. The method of claim 1 further comprising the steps of:
(C′) placing the integrated circuit into a low power mode wherein the configurable resistance is placed into a high impedance state;
(D′) exiting the integrated circuit from the low power mode wherein the configurable resistance is placed into a conductive state;
(E′) retrieving the stored combined state of the digital control signals; and
(F′) applying the stored combined state of the digital control signals to the digital resistive network.

8. The method of claim 7 wherein the reference resistor is external to the integrated circuit.

9. The method of claim 1 wherein the reference resistor is external to the integrated circuit.

10. An apparatus for self-calibrating a configurable resistance on an integrated circuit, comprising:
a first power supply node;
a second power supply node;
a reference connection node;
a reference voltage source;
a first voltage divider comprising:
a first digital resistor network coupled between the first power supply node and the reference connection node,
a first analog resistor network coupled between the first power supply node and the reference connection node, and
a reference resistor coupled between the reference connection node and the second power supply node;

a voltage comparison node;
a second voltage divider comprising:
a second digital resistor network coupled between the first power supply and the voltage comparison node,
a second analog resistor network coupled between the first power supply node and the voltage comparison node,
a third digital resistor network coupled between the voltage comparison node and the second power supply node,
a third analog resistor network coupled between the voltage comparison node and the second power supply node; and

control circuitry coupled to the reference connection node, the voltage comparison node, and the reference voltage source for configuring the configurable resistance based on the resistance of the reference resistor by tuning the digital resistor networks, and by dynamically tuning the analog resistor networks.

11. The apparatus of claim 10 , further comprising:
a first register coupled to the control logic and to the first digital resistor network and the second digital resistor network wherein the data word stored in the register controls the resistance of the first digital resistor network and the second digital resistor network;
a second register coupled to the control logic and to the third digital resistor network wherein the data word stored in the register controls the resistance of the third digital network;
a first amplifier having:
an output coupled to the control logic, the first analog resistor network and the second analog resistor network,
a first input coupled to the reference voltage source, and
a second input coupled to the reference connection node; and

a second amplifier having:
an output coupled to the control logic,
a first input coupled to the reference voltage source, and
a second input coupled to the output of the voltage comparison node.

12. The apparatus of claim 11 :
wherein the first amplifier compares the reference voltage to the voltage on the reference connection node during the tuning of the first digital resistor network, and controls the resistance of the first analog resistor network using a first feedback loop during the dynamic tuning of the first analog resistor network;
wherein the second digital resistor network is tuned by using the same data word as the first digital resistor network, and the second analog resistor network is dynamically tuned by the first feedback loop; and
wherein the second amplifier compares the reference voltage to the voltage on the voltage comparison node during the tuning of the third digital resistor network, and controls the resistance of the third analog resistor network using a first feedback loop during the dynamic tuning of the third analog resistor network.

Assignees

• Invensas Corp

Inventors

• Dicke Curtis
• Courville George
• Fisch David
• Sandusky Randall
• Stalnaker Kent

Classifications

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H01C10/50

  structurally combined with switching arrangements (H01C10/36 takes precedence) · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title