Structure and method to reduce shorting and process degradation in STT-MRAM devices

Patent metadata

Field	Value
Publication number	US-9705071-B2
Application number	US-201514950830-A
Country	US
Kind code	B2
Filing date	Nov 24, 2015
Priority date	Nov 24, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method of making a magnetic random access memory device includes forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ including a reference layer, a tunnel barrier layer, and a free layer; disposing a hard mask on the MTJ; etching sidewalls of the hard mask and MTJ to form a stack with a first width and redeposit metal along the MTJ sidewall; depositing a sacrificial dielectric layer on the hard mask, surface of the electrode, exposed sidewall of the hard mask and the MTJ, and on redeposited metal along the sidewall of the MTJ; removing a portion of the sacrificial dielectric layer from sidewalls of the hard mask and MTJ and redeposited metal from the MTJ sidewalls; and removing a portion of a sidewall of the MTJ and hard mask to provide a second width to the stack; wherein the second width is less than the first width.

First claim

What is claimed is:

1. A method of making a magnetic random access memory (MRAM) device, the method comprising:
forming a magnetic tunnel junction (MTJ) on an electrode, the MTJ comprising a reference layer disposed in contact with the electrode, a tunnel barrier layer disposed on the reference layer, and a free layer disposed on the tunnel barrier layer;
disposing a hard mask on the MTJ;
etching sidewalls of the hard mask and the MTJ to form a stack with a first width and redeposit a metal along a sidewall of the MTJ;
depositing a sacrificial dielectric layer on a surface of the hard mask, a surface of the electrode, an exposed sidewall of the hard mask and the MTJ, and on redeposited metal positioned along the sidewall of the MTJ; and
performing a directional etch to substantially remove the sacrificial dielectric layer from sidewalls of the hard mask and the MTJ, the redeposited metal from sidewalls of the MTJ, and portions of sidewalls of the MTJ and hard mask to provide a second width to the stack;
wherein a top surface of the sacrificial dielectric layer remains substantially intact during the directional etch, and the second width of the stack is less than the first width.

2. The method of claim 1 , further comprising depositing an encapsulating dielectric layer on the sacrificial dielectric layer.

3. The method of claim 1 , wherein removing a portion of the sacrificial dielectric layer redeposits a portion of the sacrificial dielectric layer on a sidewall of the MTJ.

4. The method of claim 3 , further comprising depositing an encapsulating dielectric layer on redeposited portions of the sacrificial dielectric layer.

5. The method of claim 4 , wherein the encapsulating dielectric layer is disposed directly on exposed sidewalls of the hard mask.

6. The method of claim 1 , wherein the sacrificial dielectric layer is a dielectric oxide a dielectric nitride, a dielectric oxynitride, an aluminum oxide, or any combination thereof.

7. The method of claim 1 , wherein depositing the sacrificial dielectric layer comprises using a physical vapor deposition (PVD) method at a temperature in a range from about 25 to about 300° C.

8. The method of claim 1 , wherein depositing the sacrificial dielectric layer comprises using a plasma enhanced chemical vapor deposition method (PECVD) to deposit a silicon nitride film.

Assignees

• IBM

Inventors

• Annunziata Anthony J
• Lauer Gen P
• Nowak Janusz J
• O'Sullivan Eugene J

Classifications

• H01L43/02 Primary

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic

• H10N50/80

  Constructional details · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title