Vertical FET with strained channel

Patent metadata

Field	Value
Publication number	US-9704990-B1
Application number	US-201615269180-A
Country	US
Kind code	B1
Filing date	Sep 19, 2016
Priority date	Sep 19, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transistor. In one or more embodiments, an initial transistor structure is formed including a substrate, a dummy fin, and a hard mask. The dummy fin structure is narrowed. A channel is epitaxially grown on the dummy fin structure to create a strain on the channel. A first gate stack is formed over the channel. The hard mask and dummy fin are removed. A second gate stack is formed over the channel. Excess material is removed from the second gate stack. The formation of the transistor is finalized using a variety of techniques.

First claim

What is claimed is:

1. A method of forming a transistor in an integrated circuit device, the method comprising:
forming an initial transistor structure including a substrate, a dummy fin, and a hard mask;
reducing a width dimension of the dummy fin structure;
epitaxially growing a channel on the dummy fin structure to create a strain on the channel;
forming a first gate stack adjacent to the channel;
removing the hard mask and dummy fin;
forming a second gate stack over the channel; and
removing excess material from the second gate stack.

2. The method of claim 1 wherein:
the dummy fin comprises silicon; and
the epitaxially grown channel comprises silicon germanium; wherein:
a lattice mismatch between silicon and silicon germanium causes the silicon germanium channel to have a compressive strain.

3. The method of claim 1 wherein:
the dummy fin comprises silicon germanium; and
the epitaxially grown channel comprises silicon; wherein:
a lattice mismatch between silicon and silicon germanium causes the silicon channel to have a tensile strain.

4. The method of claim 1 wherein:
the hard mask comprises an oxide and a nitride.

5. The method of claim 1 wherein:
the first gate stack comprises a first high-k material which is below a first work function metal, which is below a first gate material.

6. The method of claim 5 wherein:
the second gate stack comprises a second high-k material which is below a second work function metal, which is below a second gate material.

7. The method of claim 5 wherein:
the first gate stack further comprises a bottom spacer below the first high-k material.

8. The method of claim 5 wherein the first gate material is selected from a polysilicon or a tungsten-based material.

9. The method of claim 1 wherein:
removing the hard mask and dummy fin comprises using a selective etch technique to remove the hard mask and dummy fin without affecting the channel.

10. The method of claim 1 further comprising:
placing a bottom spacer over the substrate prior to epitaxially growing the channel on the dummy fin structure.

Assignees

• IBM

Inventors

• Mochizuki Shogo
• Wang Junli

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/01356

  the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence) · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H01L21/3081

  Electricity · mapped topic