Super-junction semiconductor device comprising junction termination extension structure and method of manufacturing

Patent metadata

Field	Value
Publication number	US-9704984-B2
Application number	US-201615139664-A
Country	US
Kind code	B2
Filing date	Apr 27, 2016
Priority date	Apr 29, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A super-junction semiconductor device includes a junction termination area at a first surface of a semiconductor body and at least partly surrounding an active cell area. An inner part of the junction termination area is arranged between an outer part of the junction termination area and the active cell area. A charge compensation device structure includes first regions of a first conductivity type and second regions of a second conductivity type disposed alternately along a first lateral direction. First surface areas correspond to a projection of the first regions onto the first surface, and second surface areas correspond to a projection of the second regions onto the first surface. The super-junction semiconductor device further includes at least one of a first junction termination extension structure and a second junction termination extension structure.

First claim

What is claimed is:

1. A super-junction semiconductor device, comprising:
a junction termination area at a first surface of a semiconductor body and at least partly surrounding an active cell area, wherein an inner part of the junction termination area is arranged between an outer part of the junction termination area and the active cell area;
a charge compensation device structure comprising first regions of a first conductivity type and second regions of a second conductivity type disposed alternately along a first lateral direction, first surface areas corresponding to a projection of the first regions onto the first surface, and second surface areas corresponding to a projection of the second regions onto the first surface; and
at least one of a first junction termination extension structure and a second junction termination extension structure, wherein first dopants of the first conductivity type constitute the first junction termination extension structure, wherein, in the outer part of the junction termination area, a projection area of the first junction termination extension structure onto the first surface is at least partly included in the second surface areas and is at least partly excluded from the first surface areas, and second dopants of the second conductivity type constitute the second junction termination extension structure, wherein, in the inner part of the junction termination area, a projection area of the second junction termination extension structure onto the first surface is at least partly included in the first surface areas and is at least partly excluded from the second surface areas.

2. The super-junction semiconductor device of claim 1 , wherein the second dopants are absent in the outer part of the junction termination area.

3. The super-junction semiconductor device of claim 1 , wherein the first dopants are absent in the inner part of the junction termination area.

4. The super-junction semiconductor device of claim 1 , wherein the charge compensation device structure and the first junction termination extension structure are absent in the outer part of the junction termination area.

5. The super-junction semiconductor device of claim 1 , wherein the charge compensation device structure and the second junction termination extension structure are absent in the inner part of the junction termination area.

6. The super-junction semiconductor device of claim 1 , wherein an intermediate part of the junction termination area is arranged between the outer and inner parts of the junction termination area, and wherein, in the intermediate part of the junction termination area, a projection area of the first junction termination extension structure onto the first surface is at least partly included in the second surface areas and is at least partly excluded from the first surface areas, and a projection area of the second junction termination extension structure onto the first surface is at least partly included in the first surface areas and is at least partly excluded from the second surface areas.

7. The super-junction semiconductor device of claim 1 , wherein an element of the first dopants and an element of the dopants constituting the first regions are different.

8. The super-junction semiconductor device of claim 1 , wherein an element of the second dopants and an element of the dopants constituting the second regions are different.

9. The super-junction semiconductor device of claim 1 , wherein source regions electrically connected by contacts at the first surface in the active cell area are absent in the junction termination area.

10. The super-junction semiconductor device of claim 1 , further comprising:
a source contact at the first surface and electrically connected to a source region in the semiconductor body; and
a drain contact at a second surface of the semiconductor body opposite to the first surface, the drain contact being electrically connected to a drain region in the semiconductor body.

11. The super-junction semiconductor device of claim 1 , wherein the active cell area is completely surrounded by the junction termination area.

12. The super-junction semiconductor device of claim 1 , wherein the active cell area comprises a plurality or transistor cells connected in parallel.

13. The super-junction semiconductor device of claim 1 , wherein an extension of the junction termination area along the lateral direction ranges between 30 μm and 1000 μm.

14. The super-junction semiconductor device of claim 1 , wherein a dose of the second dopants ranges between 5×10 11 cm −2 and 5×10 12 cm −2 .

15. The super-junction semiconductor device of claim 1 , wherein the junction termination area has an outermost part, wherein the outer part is arranged between the outermost part and the inner part, and wherein, in the outermost part of the junction termination area, a projection area of the first junction termination extension structure onto the first surface is at least partly included in the second surface areas and is at least partly included in the first surface areas.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Hirler Franz
• Tutuc Daniel
• Voerckel Andreas
• Weber Hans

Classifications

• H10D62/058

  by using trenches, e.g. implanting into sidewalls of trenches or refilling trenches · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H01L29/7811 Primary

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic

• H01L29/0615

  Electricity · mapped topic