Semiconductor structure having buried gate structure, method for manufacturing the same, and memory cell having the same

Patent metadata

Field	Value
Publication number	US-9704961-B2
Application number	US-201615090759-A
Country	US
Kind code	B2
Filing date	Apr 5, 2016
Priority date	Oct 29, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A method for forming a semiconductor structure includes forming a trench in a semiconductor substrate; forming a gate dielectric layer over a bottom surface and sidewalls of the trench; forming a work function layer over the gate dielectric layer; recessing the work function layer, and forming a gate electrode which is positioned in the trench; and exposing the gate electrode to a thermal process, and forming a dipole induction layer between the gate electrode and the gate dielectric layer.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
forming a trench in a semiconductor substrate;
forming a gate dielectric layer over a bottom surface and sidewalls of the trench;
forming a work function layer over the gate dielectric layer;
recessing the work function layer to form a gate electrode which is recessed in the trench; and
exposing the gate electrode to a thermal process to form a dipole induction layer between the gate electrode and the gate dielectric layer,
wherein an oxygen areal density of the dipole induction layer is higher than an oxygen areal density of the gate dielectric layer.

2. The method according to claim 1 , wherein the thermal process is performed in an oxygen-free atmosphere.

3. The method according to claim 1 , wherein the forming of the dipole induction layer is performed by rapid thermal annealing.

4. The method according to claim 3 , wherein the rapid thermal annealing is performed in a nitrogen or argon atmosphere.

5. The method according to claim 1 , wherein the work function layer and the dipole induction layer includes same metal atom.

6. The method according to claim 1 , wherein the work function layer comprises a metal-base material, and the dipole induction layer comprises oxide which contains a metal of the metal-base material.

7. The method according to claim 1 , wherein the work function layer comprises titanium nitride, and
wherein the dipole induction layer comprises titanium oxide.

8. A method for forming a semiconductor structure, comprising:
forming a trench in a semiconductor substrate;
forming a gate dielectric layer over a bottom surface and sidewalls of the trench;
forming a work function layer over the gate dielectric layer;
recessing the work function layer to form a gate electrode which is recessed in the trench; and
exposing the gate electrode to a thermal process to form a dipole induction layer between the gate electrode and the gate dielectric layer,
wherein the forming of the work function layer comprises:
forming conformally a first work function layer over the gate dielectric layer; and
filling a second work function layer over the first work function layer,
wherein the dipole induction layer is formed by a reaction of a portion of the first work function layer and a portion of the gate dielectric layer.

9. The method according to claim 8 , wherein the first work function layer comprises titanium nitride, and
wherein the second work function layer comprises tungsten.

10. The method according to claim 8 , wherein each of the first work function layer and the second work function layer comprises titanium nitride.

11. The method according to claim 1 , wherein the gate dielectric layer comprises silicon oxide,
wherein the work function layer comprises titanium nitride, and
wherein the dipole induction layer comprises titanium oxide.

12. A method for forming a semiconductor structure, comprising:
forming a trench in a semiconductor substrate;
forming a gate dielectric layer over a bottom surface and sidewalls of the trench;
forming a first work function layer over the gate dielectric layer;
exposing the first work function layer to a thermal process to form a pre-dipole induction layer between the first work function layer and the gate dielectric layer;
forming a second work function layer over the first work function layer to fill the trench;
recessing the second work function layer and the first work function layer to form a second work function portion and a first work function portion in the trench; and
recessing the pre-dipole induction layer to form a dipole induction layer between the first work function portion and the gate dielectric layer,
wherein an oxygen areal density of the pre-dipole induction layer is higher than an oxygen areal density of the gate dielectric layer.

13. The method according to claim 12 , wherein the thermal process is performed in an oxygen-free atmosphere.

14. The method according to claim 12 , wherein the forming of the dipole induction layer is performed by rapid thermal annealing.

15. The method according to claim 14 , wherein the rapid thermal annealing is performed in a nitrogen or argon atmosphere.

16. The method according to claim 12 , wherein the first work function layer comprises titanium nitride, and
wherein the dipole induction layer comprises titanium oxide.

17. The method according to claim 12 , further comprising:
after the forming of the dipole induction layer,
forming a third work function layer over the first work function portion and the second work function portion;
recessing the third work function layer to form a third work function portion;
forming a capping layer over the third work function portion; and
introducing a dopant into the semiconductor substrate by using the capping layer as a barrier to form doping regions which overlap the third work function portion.

18. The method according to claim 17 , wherein each of the doping regions does not overlap with the dipole induction layer.

19. The method according to claim 17 , wherein the third work function layer has a work function lower than the first work function layer and the second work function layer.

20. The method according to claim 12 , wherein the pre-dipole induction layer is formed by an oxidation of a portion of the first work function layer.

Assignees

• Sk Hynix Inc

Inventors

• Jang Tae-Su

Classifications

• H10P14/69394

  the material containing titanium, e.g. TiO2 · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L27/10876

  Electricity · mapped topic