Semiconductor structure and method of making

Patent metadata

Field	Value
Publication number	US-9704830-B1
Application number	US-201614994702-A
Country	US
Kind code	B1
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A semiconductor structure in the form of a die comprises a silicon-containing core having a first surface, an opposite second surface and a peripheral edge surface. A circuit structure on the first surface is circumscribed by a peripheral crackstop structure which stops short of the second surface, thereby leaving an accessible portion of the peripheral edge surface free of the crackstop structure. One or more angular or orthogonal edge connector through-silicon conductive vias (“edge connector TSVs”) connect the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure. A method of making the structure includes forming the edge connector TSVs in the silicon wafer from which the semiconductor structures, i.e., dies, are cut.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a silicon-containing substrate having a first surface on which is disposed a circuit structure, a second surface, and a peripheral edge surface;
a peripheral crackstop structure circumscribing the circuit structure and extending along a portion of the peripheral edge surface adjacent to the first surface and stopping short of the second surface, to thereby leave an accessible portion of the peripheral edge surface free of the crackstop structure; and
one or more edge connector through-silicon conductive vias (“edge connector TSVs”) connecting the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure.

2. The semiconductor structure of claim 1 wherein the one or more edge connector TSVs are angular edge connector TSVs, at least a segment of the angular edge connector TSVs extending through the substrate at an acute angle relative to the first surface.

3. The semiconductor structure of claim 2 wherein the entirety of at least one of the angular edge connector TSVs extends at an acute angle relative to the first surface.

4. The semiconductor structure of claim 1 wherein the one or more edge connector TSVs have at least a first leg and a second leg, the first leg extending perpendicularly to the first surface through the substrate to the second leg, and the second leg extending along the second surface to the accessible portion of the peripheral edge surface.

5. The semiconductor structure of claim 4 wherein the second leg is accessible at the second surface.

6. An array of interconnected semiconductor structures, at least one of which comprises the semiconductor structure of claim 1 .

7. An array of interconnected semiconductor structures comprising a plurality of the semiconductor structure of claim 1 .

8. The array of claim 7 mounted on a support member to provide a semiconductor assembly with respective ones of the edge connector TSVs connected to one or both of other edge connector TSVs and other elements of the assembly.

9. A semiconductor structure comprising:
a silicon-containing substrate having a first surface on which is disposed a circuit structure circumscribed by a peripheral crackstop structure, an opposite second surface and a peripheral edge surface, the peripheral crackstop structure being disposed on the peripheral edge surface and extending from the first surface towards the second surface but stopping short of the second surface to thereby leave an accessible portion of the peripheral edge surface free of the crackstop structure;
one or more edge connector through-silicon conductive vias (“edge connector TSVs”) connecting the circuit structure to the accessible portion of the peripheral edge surface without penetrating the crackstop structure;
wherein the one or more edge connector TSVs are selected from the group consisting of (1) angular edge connector TSVs characterized by having at least a segment thereof extending through the substrate at an acute angle relative to the first surface and extending to the accessible portion of the peripheral edge surface; and (2) orthogonal edge connector TSVs characterized by having at least a first leg and a second leg, the first leg extending substantially perpendicularly to the first surface through the substrate to the second leg, and the second leg extending along the second surface to the accessible portion of the peripheral edge surface.

10. A plurality of interconnected semiconductor structures, at least one of which comprises the semiconductor structure of claim 9 .

11. A method of making a plurality of semiconductor structures, the method comprising providing a silicon wafer having a top surface having thereon a plurality of mounting areas adapted to receive respective circuit structures, an opposite bottom surface, and a plurality of peripheral crackstop structures extending about associated ones of the mounting areas and extending from the top surface towards the bottom surface but stopping short of the bottom surface, forming in the wafer a plurality of conductive through-silicon vias (“TSVs”) extending from respective ones of the mounting areas, and dicing the wafer along dicing pathways to form a plurality of dies having respective opposite first and second surfaces and peripheral edge surfaces which cooperate to define a core of the die.

12. The method of claim 11 wherein the crackstop structures extend below the top surface of the wafer and stop short of the bottom surface of the wafer whereby the peripheral edge surfaces of the dies comprise accessible portions through which the core of the die is accessible without penetrating the crackstop structure, and configuring at least some of the TSVs as edge connector TSVs which extend from respective ones of the mounting areas to locations on the dicing pathways which are free of the crackstop structures, whereby when such dies are cut from the wafer the edge connector TSVs terminate at accessible portions of the peripheral edge surfaces of the dies without penetrating the crackstop structure.

13. The method of claim 12 wherein the improvement further comprises configuring at least some of the edge connector TSVs as angular edge connector TSVs, at least a segment of the angular edge connector TSVs extending through the wafer at an acute angle relative to the first and second major surfaces of the dies.

14. The method of claim 12 wherein the improvement further comprises configuring at least some of the edge connector TSVs as orthogonal edge connector TSVs having a first leg which extends to the second surface of the die perpendicularly to the first surface, and a second leg connected to the first leg, the second leg being accessible at and extending along the bottom surface of the die to the accessible portion of the peripheral edge surfaces.

15. The method of claim 14 wherein the improvement further comprises applying a dielectric to the accessible second legs of the edge connector TSVs.

16. The method of claim 12 further comprising disposing respective circuit structures on respective mounting areas and connecting the circuit structures to the edge connector TSVs.

Assignees

• IBM

Inventors

• Ayotte Stephen P
• Richard Glen E
• Sullivan Timothy M

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title