Oxidation resistant barrier metal process for semiconductor devices

Patent metadata

Field	Value
Publication number	US-9704804-B1
Application number	US-201514974012-A
Country	US
Kind code	B1
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

First claim

What is claimed is:

1. A process of forming an integrated circuit, comprising the steps:
forming an underlying metal geometry on a first dielectric;
depositing a second dielectric layer over the underlying metal geometry and over the first dielectric;
forming a contact photo resist pattern on the second dielectric layer with a contact opening over the underlying metal geometry;
etching a contact opening through the second dielectric layer and stopping on the underlying metal geometry;
depositing an overlying metal layer in the contact opening in the second dielectric layer;
forming an oxidation resistant barrier layer between the underlying metal geometry and the overlying metal layer wherein the oxidation resistant barrier layer is tantalum nitride (TaN) or titanium nitride (TiN) with a nitrogen content of at least 20 atomic percent and a thickness of at least 5 nm;
forming a photo resist pattern on the overlying metal layer with a geometry covering the contact opening; and
etching the overlying metal layer with the photo resist pattern to form an overlying metal geometry.

2. The process of claim 1 , wherein forming the oxidation resistant barrier layer comprises depositing an oxidation resistant barrier layer on the second dielectric layer and on the sides and bottom of the contact opening.

3. The process of claim 2 , wherein the oxidation resistant barrier layer is deposited on the underlying metal geometry prior to depositing the second dielectric layer.

4. The process of claim 1 further comprising the step of exposing the oxidation resistant barrier layer to air for a period of time up to 24 hours prior to the step of depositing the overlying metal layer.

5. The process of claim 1 further comprising the step of depositing an interdiffusion barrier layer prior to the step of depositing the oxidation resistant barrier layer.

6. The process of claim 5 , wherein the interdiffusion barrier layer is a TaN or TiN layer with a thickness between 60 nm and 90 nm and a nitrogen content in the range of 0 to 12 atomic percent.

7. The process of claim 1 , wherein the oxidation resistance barrier layer is a TaN layer with a thickness in the range of 5 nm to 15 nm and a nitrogen content in the range of 20 to 35 atomic percent.

8. The process of claim 1 , wherein the oxidation resistant barrier layer is TaN with a thickness in the range of 5 nm to 15 nm deposited at room temperature with a pressure between about 2.5 to 5 torr, a power in the range of 15 to 30 KW, a bias in the range of 250 W to 500 W, and a flow rate of nitrogen in the range of about 115 to 125 sccm.

9. A process of forming an integrated circuit, comprising the steps:
depositing an underlying metal layer on a first dielectric layer;
depositing an oxidation resistant barrier layer on the underlying metal layer wherein the oxidation resistant barrier layer is TaN or TiN with a nitrogen content of at least 20 atomic percent and a thickness of at least 5 nm;
forming a photo resist pattern on the oxidation resistant barrier layer;
etching the oxidation resistant barrier layer and etching the underlying metal layer to form an underlying metal geometry;
depositing a second dielectric layer over the underlying metal geometry and over the first dielectric layer;
forming a contact photo resist pattern on the second dielectric layer with a contact opening over the underlying metal geometry;
etching a contact opening through the second dielectric layer and stopping on the oxidation resistant barrier layer on the underlying metal geometry;
depositing an overlying metal layer wherein the overlying metal layer fills the contact opening in the second dielectric layer;
forming a photo resist pattern on the overlying metal layer; and
etching the overlying metal layer to form an overlying metal geometry which covers the contact opening in the second dielectric layer.

10. The process of claim 9 , wherein the oxidation resistant barrier layer is TaN with a thickness in the range of 5 nm to 15 nm deposited at room temperature with a pressure between about 2.5 to 5 torr, a power in the range of 15 to 30 KW, a bias in the range of 250 W to 500 W, and a flow rate of nitrogen in the range of about 115 to 125 sccm.

11. The process of claim 9 , further comprising the step of depositing an interdiffusion barrier layer prior to the step of depositing the oxidation resistant barrier layer.

12. The process of claim 11 , wherein the interdiffusion barrier layer is a TaN or TiN layer with a thickness between 60 nm and 90 nm and a nitrogen content in the range of 0 to 12 atomic percent.

13. The process of claim 9 , wherein the oxidation resistance barrier layer is a TaN layer with a thickness in the range of 5 nm to 15 nm and a nitrogen content in the range of 20 to 35 atomic percent.

14. A process of forming an integrated circuit, comprising the steps:
forming an underlying metal geometry over a first dielectric;
depositing a second dielectric layer over the first dielectric;
etching a contact opening through the second dielectric layer;
depositing an overlying metal layer in the contact opening;
forming an oxidation resistant barrier layer between the underlying metal geometry and the overlying metal layer wherein the oxidation resistant barrier layer is TaN or TiN with a nitrogen content of at least 20 atomic percent and a thickness of at least 5 nm; and
etching the overlying metal layer to form an overlying metal geometry.

15. The process of claim 14 , wherein forming the oxidation resistant barrier layer comprises depositing an oxidation resistant barrier layer on the second dielectric layer and on the sides and bottom of the contact opening.

16. The process of claim 14 , wherein the oxidation resistant barrier layer is deposited on the underlying metal geometry prior to depositing the second dielectric layer.

17. The process of claim 14 , further comprising the step of exposing the oxidation resistant barrier layer to air for a period of time up to 24 hours prior to the step of depositing the overlying metal layer.

18. The process of claim 14 , further comprising the step of depositing an interdiffusion barrier layer prior to the step of depositing the oxidation resistant barrier layer.

19. The process of claim 18 , wherein the interdiffusion barrier layer is a TaN or TiN layer with a thickness between 60 nm and 90 nm and a nitrogen content in the range of 0 to 12 atomic percent.

20. The process of claim 14 , wherein the oxidation resistant barrier layer is a TaN layer with a thickness in the range of 5 nm to 15 nm and a nitrogen content in the range of 20 to 35 atomic percent.

Assignees

• Texas Instruments Inc

Inventors

• West Jeffrey A
• Udayakumar Kezhakkedath R
• Warninghoff Eric H
• Merriam Alan G
• Faust Rick A

Classifications

• H10W72/019

  of bond pads · CPC title

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title