Direct selective adhesion promotor plating

Patent metadata

Field	Value
Publication number	US-9704786-B2
Application number	US-201514866050-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A lead frame strip having a plurality of unit lead frames is provided. Each of the unit lead frames includes a die paddle, a plurality of leads extending away from the die paddle, and a peripheral ring delineating interior portions of the leads from exterior portions of the leads. An adhesion promoter plating material is selectively plated within a package outline area of a first unit lead frame. The die paddle and the interior portions of the leads are disposed within the package outline area and the exterior portions of the leads are disposed outside of the package outline area. Wire bond sides are processed such that, after selectively plating the adhesion promoter plating material, the wire bond sites are substantially devoid of the adhesion promoter plating material. The wire bond sites are disposed within the package outline area and are spaced apart from the peripheral ring.

First claim

What is claimed is:

1. A method of forming a packaged semiconductor device, comprising:
providing a lead frame strip having a plurality of unit lead frames, each of the unit lead frames comprising a die paddle, a plurality of leads extending away from the die paddle, and a peripheral ring delineating interior portions of the leads from exterior portions of the leads;
selectively plating an adhesion promoter plating material within a package outline area of a first unit lead frame, the die paddle and the interior portions of the leads being disposed within the package outline area and the exterior portions of the leads being disposed outside of the package outline area; and
processing wire bond sites in the first unit lead frame such that, after selectively plating the adhesion promoter plating material, the wire bond sites are substantially devoid of the adhesion promoter plating material,
wherein the wire bond sites are disposed within the package outline area and are spaced apart from the peripheral ring,
wherein selectively plating the adhesion promoter plating material to the first unit lead frame comprises:
providing a mask over the first unit lead frame, the mask covering the exterior portions of the leads and comprising openings that expose the package outline area; and
forming the adhesion promoter plating material in the openings.

2. The method of claim 1 , wherein the wire bond sites are covered by mask so as to prevent the adhesion promoter plating material from forming on the wire bond sites during the formation of the adhesion promoter plating material.

3. The method of claim 2 , wherein processing the wire bond sites is performed before or after selectively plating the adhesion promoter plating material.

4. The method of claim 3 , wherein processing the wire bond sites comprises:
prior to selectively plating the adhesion promoter plating material, chemically treating the wire bond sites so as to prevent the adhesion promoter plating material from forming on the wire bond sites during the selective application of the adhesion promoter plating material.

5. The method of claim 4 , wherein chemically treating the wire bond sites comprises exposing the wire bond sites to an anti-immersion or anti-tarnish chemical inhibitor.

6. The method of claim 3 , wherein processing the wire bond sites comprises:
after selectively plating the adhesion promoter plating material, removing portions of the adhesion promoter plating that form on the wire bond sites during formation of the adhesion promoter plating material.

7. The method of claim 6 , wherein removing portions of the adhesion promoter plating that form on the wire bond sites comprises applying a chemical cleaning solution to the wire bond sites, the chemical cleaning solution comprising at least one of: Potassium hydroxide, Ammonium acetate, Potassium lactate, and Acetone.

8. The method of claim 7 , wherein applying the chemical cleaning solution comprises a selective cleaning process that exposes the wire bond sites to the chemical cleaning solution and protects adjacent regions from the chemical cleaning solution.

9. The method of claim 3 , wherein processing the wire bond sites comprises:
after selectively plating the adhesion promoter plating material, plating the wire bond sites with a wire bondable layer so as to cover portions of the adhesion promoter plating material that form on the wire bond sites.

10. The method of claim 3 , wherein processing the wire bond sites comprises:
after selectively plating the adhesion promoter plating material, applying a laser cleaning process to the wire bond sites so as to remove any adhesion promoter plating material that leaks onto the wire bond sites.

11. The method of claim 3 , wherein processing the wire bond sites comprises:
prior to selectively plating the adhesion promoter plating material, applying a corrosion resistance coating to the lead frame, wherein the corrosion resistance prevents the adhesion promoter plating material from forming on the wire bond sites.

12. The method of claim 3 , wherein processing the wire bond sites comprises:
prior to providing the mask over the first unit lead frame, applying a tape over the wire bond sites.

13. The method of claim 3 , wherein the adhesion promoter plating material comprises a Zinc based metal.

14. The method of claim 13 , wherein the adhesion promoter plating material comprises at least one of ZnMo and ZnV.

15. A method of forming a packaged semiconductor device, comprising:
providing a lead frame strip having a plurality of unit lead frames, each of the unit lead frames having a central opening and a plurality of leads extending away from the central opening;
selectively plating an adhesion promoter plating material on a first unit lead frame within a package outline area of on first portions of the leads;
forming an electrically insulating encapsulant material on the first portions of the leads such that the central opening is enclosed by a cavity formed by outer sidewalls of the encapsulant material; and
after forming the electrically insulating encapsulant material, plating regions of the leads that exposed from the electrically insulating encapsulant with a wire bondable layer.

16. The method of claim 15 , wherein the first portions of the leads comprise an elevated portion, the elevated portion being closer to the central opening than outer portions of the leads, and wherein the outer sidewalls of the encapsulant material are formed on the elevated portions of the leads.

17. The method of claim 15 , wherein selectively plating the adhesion promoter plating material comprises a single pass plating process, the single pass plating process comprising:
proving a mask over the first unit lead frame, the mask covering the exterior portions of the leads and comprising openings that expose the elevated portions of the leads; and
forming the adhesion promoter plating material in the openings.

Assignees

• Infineon Technologies Ag

Inventors

• Dangelmaier Jochen
• Hoa Kim Huat
• Aland Abd Hamid Hazrul
• Allmeier Andreas
• Lang Dietmar

Classifications

• H10W72/534

  being rectangular · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/075

  of bond wires · CPC title