Flat No-Leads Package With Improved Contact Pins

Patent metadata

Field	Value
Publication number	US-2017294367-A1
Application number	US-201715480661-A
Country	US
Kind code	A1
Filing date	Apr 6, 2017
Priority date	Apr 7, 2016
Publication date	Oct 12, 2017
Grant date	—

Abstract

According to an embodiment of the present disclosure, a method for manufacturing an integrated circuit (IC) device may include mounting an IC chip onto a center support structure of a leadframe. The leadframe may include: a plurality of pins extending from the center support structure; a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and a bar connecting the plurality of pins remote from the center support structure. The method may further include: bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove.

First claim

1 . A method for manufacturing an integrated circuit (IC) device in a flat no-leads package, the method comprising:
mounting an IC chip onto a center support structure of a leadframe, the leadframe including:
a plurality of pins extending from the center support structure;
a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and
a bar connecting the plurality of pins remote from the center support structure;
bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; and cutting the IC package free from the bar by sawing through the encapsulated lead frame along the groove using a first saw width less than a width of the groove.

2 . A method according to claim 1 , further comprising:
performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the lead frame; and performing a circuit test of the isolated individual pins after the isolation cut.

3 . A method according to claim 1 , further comprising:
performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the bar, wherein the isolation cut is performed with a second saw width less than the width of the groove; and performing a circuit test of the isolated individual pins after the isolation cut.

4 . A method according to claim 1 , further comprising bonding the IC chip to at least some of the plurality of pins using wire bonding.

5 . A method according to claim 1 , wherein the width of the groove is approximately 0.40 mm.

6 . A method according to claim 1 , wherein the first saw width is approximately 0.30 mm.

7 . A method according to claim 3 , wherein the second saw width is between approximately 0.24 mm and 0.30 mm.

8 . A method according to claim 1 , wherein the groove is approximately 0.1 mm to 0.15 mm deep and the leadframe has a thickness of approximately 0.20 mm.

9 . A method for installing an integrated circuit (IC) device in a flat no-leads package onto a printed circuit board (PCB), the method comprising:
mounting an IC chip onto a center support structure of a leadframe, the leadframe including:
a plurality of pins extending from the center support structure;
a groove running perpendicular to the individual pins of the plurality of pins around the center support structure; and
a bar connecting the plurality of pins remote from the center support structure;
bonding the IC chip to at least some of the plurality of pins; encapsulating the leadframe and bonded IC chip, including filling the groove with encapsulation compound; removing the encapsulation compound from the groove, thereby exposing at least a portion of the individual pins of the plurality of pins; plating the exposed portion of the plurality of pins; cutting the IC package free from the bar by sawing through the encapsulated lead frame at the groove using a first saw width less than a width of the groove; and attaching the flat no-leads IC package to the PCB using a reflow soldering method to join the plurality of pins of the IC package to respective contact points on the PCB.

10 . A method according to claim 9 , further comprising:
performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the lead frame; and performing a circuit test of the isolated individual pins after the isolation cut.

11 . A method according to claim 9 , further comprising:
performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the bar, wherein the isolation cut is performed with a second saw width less than the width of the groove; and performing a circuit test of the isolated individual pins after the isolation cut.

12 . A method according to claim 9 , further comprising bonding the IC chip to at least some of the plurality of pins using wire bonding.

13 . A method according to claim 9 , wherein the width of the groove is approximately 0.40 mm.

14 . A method according to claim 9 , wherein the first saw width is approximately 0.30 mm.

15 . A method according to claim 11 , wherein the second saw width is between approximately 0.24 mm and 0.30 mm.

16 . A method according to claim 9 , wherein the groove is approximately 0.1 mm to 0.15 mm deep and the leadframe has a thickness of approximately 0.20 mm.

17 . A method according to claim 9 , wherein the reflow soldering process provides fillet heights of approximately 60% of the exposed surface of the pins.

18 . An integrated circuit (IC) device in a flat no-leads package comprising:
an IC chip mounted onto a center support structure of a leadframe and encapsulated with the leadframe to form an IC package having a bottom face and four sides; the leadframe including a set of pins extending from the center support structure, a groove running perpendicular to the individual pins of the plurality of pins around the center support structure, and a bar connecting the plurality of pins remote from the center support structure; the set of pins having faces exposed along a lower edge of the four sides of the IC package; and the groove running around a perimeter of the bottom face of the IC package, including the exposed faces of the set of pins; wherein a bottom facing exposed portion of the plurality of pins including the groove is plated.

19 . An IC device according to claim 18 , wherein the step cut is approximately 0.10 mm to 0.15 mm deep.

20 . An IC device according to claim 18 , wherein individual pins of the plurality of pins are attached to a printed circuit board with fillet heights of approximately 60%.

Assignees

• Microchip Tech Inc

Inventors

• Kitnarong Rangsun
• Punyapor Prachit
• Poolsup Pattarapon
• Kumsai Swat

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title