Semiconductor device having insulating layers containing oxygen and a barrier layer containing manganese

Patent metadata

Field	Value
Publication number	US-9704740-B2
Application number	US-201615336565-A
Country	US
Kind code	B2
Filing date	Oct 27, 2016
Priority date	Aug 15, 2008
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising:
forming a first insulating layer over a semiconductor substrate, the insulating layer containing oxygen;
forming a first wire in the first insulating layer;
forming a second insulating layer over the first insulating layer and the first wire, the second insulating layer containing oxygen;
selectively removing the second insulating layer to form a first groove and a second groove over the first insulating layer;
selectively removing the second insulating layer on the inner wall of the first groove to form a first opening exposing the first wire formed under the first groove;
forming a first metal layer over the inner wall of the first groove, the second groove and the first opening, the first metal layer containing manganese;
forming a second metal layer in the first groove, the second groove and the first opening, the second metal layer containing copper;
forming, in the second groove, a plurality of oxide structures which projects from a bottom portion of the second groove; and
performing a heat treatment to form a barrier layer between the second metal layer and the second insulating layer, the barrier layer containing manganese oxide.

2. A method according to claim 1 , wherein the plurality of oxide structures are provided in parallel with each other.

3. A method according to claim 1 , wherein the plurality of oxide structures are formed of an insulating material.

4. A method according to claim 1 , wherein the plurality of oxide structures are in contact with the barrier layer at the bottom portion of the second groove and sidewalls of the plurality of oxide structures are not in contact with the barrier layer at a sidewall portion of the second groove.

5. A method according to claim 1 , further comprising:
forming a third groove over a portion of the first insulating layer where the first wire is not formed in the process of the selectively removing the second insulating layer to form the first groove and the second groove; and

forming, in the third groove, a second opening extending downwardly from a bottom portion of the third groove in the process of the selectively removing the second insulating layer on the inner wall of the first groove to form the first opening.

6. A method according to claim 5 , wherein a third opening is formed in the third groove which extends downwardly from the bottom portion of the third groove.

7. A method according to claim 6 , wherein a width of the second opening and a width of the third opening are different from each other.

Assignees

• Fujitsu Semiconductor Ltd

Inventors

• Ochimizu Hirosato
• Tsukune Atsuhiro
• Kudo Hiroshi

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/355

  of outermost layers of multilayered die-attach connectors, e.g. material of a coating · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title