Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate

Patent metadata

Field	Value
Publication number	US-9703558-B2
Application number	US-201113991877-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 23, 2011
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.

First claim

What is claimed is:

1. A method of performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction that includes a single source writemask register operand, a destination writemask register operand, a control writemask operand, and an opcode, the method comprising of:
decoding the instruction;
executing the decoded instruction to determine a least significant bit position of the source writemask register that is a true value by determining a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at a corresponding bit position is also true, and store a true value in each bit position of the destination writemask register that is of lesser significance than the determined corresponding bit position.

2. The method of claim 1 , further comprising:
storing a false value in each bit position of the destination writemask register that is of equal or greater significance than the determined corresponding bit position.

3. The method of claim 1 , further comprising:
storing a true value in a bit position of the destination writemask register that is of equal significance to the determined corresponding bit position.

4. The method of claim 1 , wherein the registers are 16-bit registers.

5. The method of claim 1 , wherein the registers are 64-bit registers.

6. An article of manufacture comprising:
a non-transitory tangible machine-readable storage medium having stored thereon an occurrence of an instruction;
wherein the instruction's format specifies as its source operand a single source writemask register, as its destination a single destination writemask register, and a control writemask operand;
and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause a determination of a least significant bit position of the source writemask register that is a true value and storage of a true value in each bit position of the destination writemask register that is of lesser significance than a determined corresponding bit position, wherein the determination is to determine a least significant bit position of the source writemask register that is a true value further comprises determining that a value in the control writemask register at a corresponding bit position is also true.

7. The article of manufacture of claim 6 , further comprising:
storage of a false value in each bit position of the destination writemask register that is of equal or greater significance than the determined corresponding bit position.

8. The article of manufacture of claim 6 , further comprising:
storage of a true value in a bit position of the destination writemask register that is of equal significance to the determined corresponding bit position.

9. The article of manufacture of claim 6 , wherein the registers are 16-bit registers.

10. The article of manufacture of claim 6 , wherein the registers are 64-bit registers.

11. An apparatus comprising:
a hardware decoder to decode an instruction that includes a single source writemask register operand, a destination writemask register operand, a control writemask operand, and an opcode; and
execution circuitry to execute the decoded instruction to determine a least significant bit position of the source writemask register that is a true value and store a true value in each bit position of the destination writemask register that is lesser significance than a determined corresponding bit position by determining that a value in the control writemask register at a corresponding bit position is also true.

12. The apparatus of claim 11 , further comprising:
the execution circuitry to store a false value in each bit position of the destination writemask register that is of equal or greater significance than the determined corresponding bit position.

13. The apparatus of claim 11 , further comprising:
the execution circuitry to store a true value in a bit position of the destination writemask register that is of equal significance to the determined corresponding bit position.

14. The apparatus of claim 11 , wherein the registers are 16-bit registers.

Assignees

• Lee Victor W
• Kim Daehyun
• Ngai Tin-Fook
• Bharadwaj Jayashankar
• Hartono Albert
• Baghsorkhi Sara
• Vasudevan Nalini
• Intel Corp

Inventors

• Lee Victor W
• Kim Daehyun
• Ngai Tin-Fook
• Bharadwaj Jayashankar
• Hartono Albert
• Baghsorkhi Sara
• Vasudevan Nalini

Classifications

• G06F15/8007

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F15/8084

  Special arrangements thereof, e.g. mask or switch · CPC title

• G06F15/8092

  Array of vector units · CPC title

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title