Test pattern generation device, fault detection system, test pattern generation method, program and recording medium

Patent metadata

Field	Value
Publication number	US-9702927-B2
Application number	US-201314371317-A
Country	US
Kind code	B2
Filing date	Jan 9, 2013
Priority date	Jan 10, 2012
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A test pattern generation device for generating a new test pattern keeping the feature of original test patterns. The test pattern generation device includes a logic value generation unit for generating a new logic value by referring given logic values of a first bit, a second bit and a third bit and by keeping or reversing a logic value of the second bit, wherein a logic value of the first bit is the same with a logic value of a given initial test pattern or a new test pattern generated by the test pattern generation device based on the initial test pattern, wherein a logic value of the second bit is the same with a logic value of the initial test pattern, and wherein a logic value of the third bit is the same with a logic value of the initial test pattern or the new test pattern.

First claim

The invention claimed is:

1. A test pattern generation device for generating a test pattern to be inputted into a circuit under test of scan test, comprising:
a logic value generation unit for generating a new logic value by referring given logic values of a first bit, a second bit and a third bit and by keeping or reversing a logic value of the second bit; and
a storing unit for storing a logic value generated by the logic value generation unit,
wherein a logic value of the first bit is the same with a logic value of an initial test pattern which is a given test pattern or with a logic value of a new test pattern generated by the test pattern generation device based on the initial test pattern,
wherein a logic value of the second bit is the same with a logic value of the initial test pattern,
wherein a logic value of the third bit is the same with a logic value of the initial test pattern or with a logic value of the new test pattern,
wherein a logic value of the first bit is, in advance, generated by the logic value generation unit and stored in the storing unit, and
wherein the logic value generation unit generates a logic value of a bit included in a newly generated test pattern by keeping or reversing a logic value of the second bit, based on logic values of the first bit stored in the storing unit, the second bit and the third bit.

2. The test pattern generation device of claim 1 ,
wherein the first bit, the second bit and the third bit are bits to be input into pluralities of spatially adjacent scan chains or bits to be input into the circuit under test temporally continuously via a single scan chain, and
wherein the storing unit is a scan flip-flop.

3. The test pattern generation device of claim 1 ,
wherein the logic value generation unit includes:
pluralities of different combinational circuits that output logic values; and
a switch unit that switches the pluralities of different combinational circuits,
wherein, into one of the pluralities of different combinational circuits, logic values of 0 or 1 of the first bit, the second bit and the third bit are input.

4. The test pattern generation device of claim 3 , further comprising:
an extraction unit that extracts a part of or all of logic values including those of the first bit, the second bit and the third bit from logic values of the initial test pattern and/or a test pattern generated by the test pattern generation device;
a condition judgment unit that judges if number of reverse of logic values extracted by the extraction unit along spatial adjacency and/or temporal continuity reaches a predetermined number or not; and
a feedback unit that feeds a judgment result by the condition judgment unit back to the switch unit.

5. A fault detection system that detects a fault based on output from a circuit under test, comprising:
an initial input test pattern storing unit that stores a test pattern generated by a test pattern generation device as an initial input test pattern, the test pattern generation device comprising:
a logic value generation unit for generating a new logic value by referring given logic values of a first bit, a second bit and a third bit and by keeping or reversing a logic value of the second bit,
wherein a logic value of the first bit is the same with a logic value of an initial test pattern which is a given test pattern or with a logic value of a new test pattern generated by the test pattern generation device based on the initial test pattern,
wherein a logic value of the second bit is the same with a logic value of the initial test pattern, and
wherein a logic value of the third bit is the same with a logic value of the initial test pattern or with a logic value of the new test pattern;

a first extraction unit that extracts a part of or all of pluralities of output logic values outputted from the circuit under test into which the initial input test pattern is inputted in advance;
a comparison unit that compares an output logic value extracted by the first extraction unit, and an output logic value estimated to be outputted if there is no fault in the circuit under test or an output logic value estimated to be outputted if there is a specific fault in the circuit under test; and
a fault judgment unit that judges if there is a fault or not in the circuit under test based on comparison result by the comparison unit;
wherein the pluralities of output logic values are inputted into the circuit under test as a new input test pattern,
wherein each of the pluralities of logic values are stored in a storing unit which stores logic values into pluralities of individual storing units which stores a single logic value,
wherein the first extraction unit extracts a part of or all of the pluralities of output logic values stored in the storing unit, and
wherein the first extraction unit extracts a part of or all of the output logic values stored in the pluralities of individual storing units directly without passing through another individual storing unit.

6. The fault detection system of claim 5 , further comprising:
a first extraction control unit that controls the first extraction unit; and
a dummy cycle assignment unit that assigns number of dummy cycle,
wherein the first extraction control unit controls the first extraction unit not to extract the pluralities of output logic values during capture cycles which the dummy cycle assignment unit assigns as dummy cycles.

7. A test pattern generation method using a test pattern generation device for generating a test pattern to be inputted into a circuit under test of scan test, comprising:
a logic value generation step for generating a new logic value by keeping or reversing a logic value of a second bit included in an initial test pattern, which is a given test pattern, and/or a test pattern generated by the test pattern generation device based on the initial test pattern, referring to a first bit, the second bit, and a third bit included in the initial test pattern and/or the test pattern generated by the test pattern generation device; and
a storing step for storing a logic value generated in the logic value generation step,
wherein a logic value of the first bit is the same with a logic value of an initial test pattern which is a given test pattern or with a logic value of a new test pattern generated by the test pattern generation device based on the initial test pattern,
wherein a logic value of the second bit is the same with a logic value of the initial test pattern,
wherein a logic value of the third bit is the same with a logic value of the initial test pattern or with a logic value of the new test pattern,
wherein a logic value of the first bit is, in advance, generated by the logic value generation unit and stored in the storing unit, and
wherein the logic value generation unit generates a logic value of a bit included in a newly generated test pattern by keeping or reversing a logic value of the second bit, based on logic values of the first bit stored in the storing unit, the second bit and the third bit.

8. A program capable of causing a computer to execute the method of claim 7 .

9. A non-transitory computer-readable medium storing a computer program of claim 8 .

Assignees

• Kyushu Inst Technology
• Japan Science & Tech Agency

Inventors

• Sato Yasuo
• Kajihara Seiji

Classifications

• G01R31/2834 Primary

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/318307 Primary

  computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging · CPC title

• G01R31/31919

  Storing and outputting test patterns (G01R31/31924 takes precedence; arithmetic and random test patterns generator) · CPC title