Apparatus including 4-way valve for fabricating semiconductor device, method of controlling valve, and method of fabricating semiconductor device using the apparatus

US9702041B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9702041-B2
Application numberUS-201615176684-A
CountryUS
Kind codeB2
Filing dateJun 8, 2016
Priority dateJan 19, 2005
Publication dateJul 11, 2017
Grant dateJul 11, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor using atomic layer deposition in an apparatus comprising a reaction chamber, a 4-way valve, a first path connected to an a first inlet of the 4-way valve, a second path connected to a second inlet of the 4-way valve, a third path connected between a first outlet of the 4-way valve and the reaction chamber, a fourth path connected to a second outlet of the 4-way valve and bypassing the reaction chamber and a fifth path connected to the reaction chamber, the method comprising: supplying a source gas to the reaction chamber through the first path and the third path when the 4-way valve is in a first state; supplying a first purge gas through the first path to the fourth path when the 4-way valve is in a second state to purge the source gas from the first path; supplying a second purge gas to the reaction chamber through the second path and the third path to purge the source gas from the reaction chamber; and supplying a reactive gas through the fifth path to the reaction chamber. 2. The method of claim 1 , further comprising interrupting the supplying of the reactive gas, and supplying the second purge gas through the second path and the third path to the reaction chamber to purge the reactive gas from the reaction chamber. 3. The method of claim 1 , further comprising supplying a carrier gas through the first path and the third path to the reaction chamber during the supplying of the source gas through the first path and the third path to the reaction chamber. 4. The method of claim 3 , further comprising interrupting the supplying of the source gas through the first path and the third path to the reaction chamber, wherein the first purge gas is the carrier gas.

Assignees

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Classifications

  • of refractory metals or yttrium · CPC title

  • of aluminium, magnesium or beryllium · CPC title

  • using selective deposition · CPC title

  • using chemical vapour deposition [CVD] · CPC title

  • Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

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What does patent US9702041B2 cover?
An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reacti…
Who is the assignee on this patent?
Samsung Electronics Co Ltd, Genitech Inc
What technology area does this patent fall under?
Primary CPC classification C23C16/45544. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue Jul 11 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).