Method of manufacturing wiring substrate, and wiring substrate

Patent metadata

Field	Value
Publication number	US-9699916-B2
Application number	US-201514707295-A
Country	US
Kind code	B2
Filing date	May 8, 2015
Priority date	May 13, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A method of manufacturing a wiring substrate according to the present invention includes a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of forming electrically insulative dummy portions separated from the wiring layer on the first insulating layer through patterning of the second insulating layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that upper end portions of the connection terminals protrude from the third insulating layer, and lower end portions of the connection terminals are embedded in the third insulating layer.

First claim

What is claimed is:

1. A method of manufacturing a wiring substrate, comprising: a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of patterning of the second insulating layer to form electrically insulative dummy portions on the first insulating layer and spaced apart from the wiring layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals in such a manner that at least one opening exposes both at least one connection terminal and at least one dummy portion; wherein an upper end portion of the at least one connection terminal protrudes from the third insulating layer, and a lower end portion of the at least one connection terminal is embedded in the third insulating layer, such that for the at least one connection terminal an upper edge of the at least one connection terminal is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer formed between the at least one connection terminal and an adjacent connection terminal or an adjacent dummy portion, and; wherein an upper end portion of the at least one dummy portion protrudes from the third insulating layer, and a lower end portion of the at least one dummy portion is embedded in the third insulating layer, such that for the at least one dummy portion an upper edge of the at least one dummy portion is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer formed between the at least one dummy portion and an adjacent connection terminal or an adjacent dummy portion.

2. The method of manufacturing a wiring substrate according to claim 1 , wherein the third insulating layer is photosensitive, and in the step of forming the openings, the third insulating layer is subjected to exposure and development so as to form the openings having respective wall surfaces located closer to the connection terminals than to the dummy portions.

3. A method of manufacturing a wiring substrate, comprising: a step of forming a wiring layer including connection terminals on a first insulating layer; a step of forming a second insulating layer on the wiring layer and on the first insulating layer; a step of patterning of the second insulating layer to form electrically insulative dummy portions on the first insulating layer and spaced apart from the wiring layer; a step of forming a third insulating layer on the wiring layer, on the dummy portions, and on the first insulating layer; and a step of forming openings in the third insulating layer for exposing the connection terminals; wherein at least one opening exposes both at least one connection terminal and at least one dummy portion; wherein the at least one connection terminal is only partially embedded in the third insulating layer such that an upper edge of the at least one connection terminal is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer; and wherein the at least one dummy portion is only partially embedded in the third insulating layer such that an upper edge of the at least one dummy portion is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer.

4. A wiring substrate comprising: a first insulating layer; a wiring layer including connection terminals formed on the first insulating layer; electrically insulative dummy portions formed on the first insulating layer and spaced apart from the wiring layer; and a third insulating layer laminated on the wiring layer, on the dummy portions, and on the first insulating layer and having openings formed therein for exposing the connection terminals with at least one opening exposing both at least one connection terminal and at least one dummy portion; wherein an upper end portion of the at least one connection terminal protrudes from the third insulating layer, and a lower end portion of the at least one connection terminal is embedded in the third insulating layer, such that for the at least one connection terminal an upper edge of the at least one connection terminal is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer formed between the at least one connection terminal and an adjacent connection terminal or an adjacent dummy portion; and wherein an upper end portion of the at least one dummy portion protrudes from the third insulating layer, and a lower end portion of the at least one dummy portion is embedded in the third insulating layer, such that for the at least one dummy portion an upper edge of the at least one dummy portion is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer formed between the at least one dummy portion and an adjacent connection terminal or an adjacent dummy portion.

5. The wiring substrate of claim 4 , wherein the electrically insulative dummy portions are formed in a region of the first insulating layer having less surface area covered by the wiring layer than an other region of the first insulating layer.

6. A wiring substrate comprising: a first insulating layer; a wiring layer including connection terminals formed on the first insulating layer; electrically insulative dummy portions formed on the first insulating layer and spaced apart from the wiring layer; and a third insulating layer laminated on the wiring layer, on the dummy portions, and on the first insulating layer and having openings formed therein for exposing the connection terminals with at least one opening exposing both at least one connection terminal and at least one dummy portion; wherein the at least one connection terminal is only partially embedded in the third insulating layer such that an upper edge of the at least one connection terminal is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer; and wherein the at least one dummy portion is only partially embedded in the third insulating layer such that an upper edge of the at least one dummy portion is located further from the first insulating layer than an upper surface of at least a part of the third insulating layer.

7. The wiring substrate of claim 6 , wherein the electrically insulative dummy portions are formed in a region of the first insulating layer having less surface area covered by the wiring layer than an other region of the first insulating layer.

Assignees

• Ngk Spark Plug Co

Inventors

• Hayashi Takahiro

Classifications

• H05K2203/0597

  Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating · CPC title

• Y10T29/49156

  with selective destruction of conductive paths · CPC title

• H05K2203/058

  Additional resists used for the same purpose but in different areas, i.e. not stacked · CPC title

• H05K2203/0307

  Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites · CPC title

• H05K3/4602

  characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated · CPC title