Dynamic clock synchronization

Patent metadata

Field	Value
Publication number	US-9698796-B2
Application number	US-201615198303-A
Country	US
Kind code	B2
Filing date	Jun 30, 2016
Priority date	Jul 17, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A semiconductor device includes: a clock synchronizing circuit that operates in synchronization with a clock; an enable signal generating circuit that generates an enable signal in an operation period during which the clock synchronizing circuit is operated; and a clock supplying circuit that supplies a clock to the clock synchronizing circuit or stop the supply of the clock according to the enable signal when a clock frequency is equal to or lower than a predetermined frequency, and supply a clock to the clock synchronizing circuit, irrespective of the enable signal, when the clock frequency is higher than the predetermined frequency.

First claim

What is claimed is:

1. A semiconductor device comprising:
a clock synchronizing circuit that operates in synchronization with a first clock;
an enable signal generating circuit that generates an enable signal in an operation period during which the clock synchronizing circuit is operated; and
a clock supplying circuit that
supplies a second clock to the clock synchronizing circuit or stops supplying the second clock to the clock synchronizing circuit according to the enable signal when a frequency of the first clock is equal to or lower than a predetermined frequency, and
supplies the second clock to the clock synchronizing circuit, irrespective of the enable signal, when the frequency of the first clock is higher than the predetermined frequency.

2. The semiconductor device according to claim 1 , wherein the clock supplying circuit includes:
an enable signal control circuit that
outputs a clock control signal in a valid or invalid state based on the enable signal received from the enable signal generating circuit when the frequency of the first clock is equal to or lower than the predetermined frequency, and
sets the clock control signal to be valid when the frequency of the first clock is higher than the predetermined frequency.

3. The semiconductor device according to claim 1 , further comprising:
a plurality of circuit blocks, each of which includes the clock synchronizing circuit, the enable signal generating circuit, and the clock supplying circuit,
wherein the predetermined frequency is set for each of the plurality of circuit blocks based on a timing margin of the clock supplying circuit for controlling the supplying of the second clock to the clock synchronizing circuit or the stopping of the supply of the second clock to the clock synchronizing circuit according to the enable signal.

4. The semiconductor device according to claim 1 , further comprising:
a frequency setting table that includes frequency information having different values for different clock frequencies, and outputs one value of the frequency information based on a frequency signal indicating a set value of the frequency of the first clock; and
a clock generating circuit that generates the first clock by the frequency information output from the frequency setting table,
wherein the clock supplying circuit detects whether or not the frequency of the first clock is the predetermined frequency by using the frequency information output from the frequency setting table.

5. The semiconductor device according to claim 4 , further comprising:
a test switch that outputs one of the values of the frequency information to the clock supplying circuit based on a switch control signal; and
a switch control circuit that generates the switch control signal based on a switch setting signal, stores a value of the switch control signal based on a switch program signal, and outputs the stored switch control signal.

6. The semiconductor device according to claim 5 , wherein the test switch is commonly coupled to the clock supplying circuit having the same predetermined frequency determined based on a timing margin of the clock supplying circuit.

7. A method for controlling a semiconductor device including a clock synchronizing circuit that operates in synchronization with a first clock, an enable signal generating circuit, and a clock supplying circuit, the method comprising:
generating, by the enable signal generating circuit, an enable signal in an operation period during which the clock synchronizing circuit is operated;
supplying, by the clock supplying circuit, a second clock to the clock synchronizing circuit or stopping the supply of the second clock to the clock synchronizing circuit according to the enable signal when a frequency of the first clock is equal to or lower than a predetermined frequency; and
supplying, by the clock supplying circuit, the second clock to the clock synchronizing circuit, irrespective of the enable signal, when the frequency of the first clock is higher than the predetermined frequency.

Assignees

• Fujitsu Ltd

Inventors

• Sekiguchi Hideyuki

Classifications

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H03L3/00

  Starting of generators · CPC title

• H03L7/00 Primary

  Automatic control of frequency or phase; Synchronisation · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title