Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9698275-B2
Application number	US-201514937147-A
Country	US
Kind code	B2
Filing date	Nov 10, 2015
Priority date	Jul 8, 2011
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer; and
a gate electrode layer comprising a region overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer,
wherein energy at a bottom of a conduction band of the second oxide semiconductor layer is lower than energy at a bottom of a conduction band of the first oxide semiconductor layer and energy at a bottom of a conduction band of the third oxide semiconductor layer,
wherein the bottom of the conduction band of the first oxide semiconductor layer and the bottom of the conduction band of the second oxide semiconductor layer are continuously connected in an energy band diagram,
wherein the bottom of the conduction band of the second oxide semiconductor layer and the bottom of the conduction band of the third oxide semiconductor layer are continuously connected in the energy band diagram, and
wherein the third oxide semiconductor layer covers and is in contact with a side surface of the first oxide semiconductor layer and a top surface and a side surface of the second oxide semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer.

3. The semiconductor device according to claim 1 , wherein an electron affinity of the second oxide semiconductor layer is higher than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the second oxide semiconductor layer comprises a crystal including a c-axis alignment.

5. The semiconductor device according to claim 1 ,
wherein the second oxide semiconductor layer comprises a crystal including a region, and
wherein a c-axis of the region of the crystal is aligned in a direction perpendicular to a surface of the second oxide semiconductor layer.

6. The semiconductor device according to claim 1 ,
wherein the second oxide semiconductor layer comprises a crystal including a region, and
wherein a c-axis of the region of the crystal is aligned so that an angle formed between the c-axis and a surface of the second oxide semiconductor layer is greater than or equal to 85° and less than or equal to 95°.

7. The semiconductor device according to claim wherein the gate electrode layer is located over the third oxide semiconductor layer.

8. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer;
a source electrode layer in contact with the third oxide semiconductor layer;
a drain electrode layer in contact with the third oxide semiconductor layer; and
a gate electrode layer comprising a region overlapping with the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer,
wherein energy at a bottom of a conduction band of the second oxide semiconductor layer is lower than energy at a bottom of a conduction band of the first oxide semiconductor layer and energy at a bottom of a conduction band of the third oxide semiconductor layer,
wherein the bottom of the conduction band of the first oxide semiconductor layer and the bottom of the conduction band of the second oxide semiconductor layer are continuously connected in an energy band diagram,
wherein the bottom of the conduction band of the second oxide semiconductor layer and the bottom of the conduction band of the third oxide semiconductor layer are continuously connected in the energy band diagram, and
wherein the third oxide semiconductor layer covers and is in contact with a side surface of the first oxide semiconductor layer and a top surface and a side surface of the second oxide semiconductor layer.

9. The semiconductor device according to claim 8 , wherein each of the source electrode layer and the drain electrode layer is in contact with a side surface of the third oxide semiconductor layer.

10. The semiconductor device according to claim 8 , wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third oxide semiconductor layer.

11. The semiconductor device according to claim 8 , wherein an electron affinity of the second oxide semiconductor layer is higher than an electron affinity of the first oxide semiconductor layer and an electron affinity of the third oxide semiconductor layer.

12. The semiconductor device according to claim 8 , wherein the second oxide semiconductor layer comprises a crystal including a c-axis alignment.

13. The semiconductor device according to claim 8 ,
wherein the second oxide semiconductor layer comprises a crystal including a region, and
wherein a c-axis of the region of the crystal is aligned in a direction perpendicular to a surface of the second oxide semiconductor layer.

14. The semiconductor device according to claim 8 ,
wherein the second oxide semiconductor layer comprises a crystal including a region, and
wherein a c-axis of the region of the crystal is aligned so that an angle formed between the c-axis and a surface of the second oxide semiconductor layer is greater than or equal to 85° and less than or equal to 95°.

15. The semiconductor device according to claim 8 , wherein the gate electrode layer is located over the third oxide semiconductor layer.

16. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode layer in contact with the second oxide semiconductor layer;
a drain electrode layer in contact with the second oxide semiconductor layer; and
a gate electrode layer over the first oxide semiconductor layer and the second oxide semiconductor layer,
wherein energy gaps of the first oxide semiconductor layer and the second oxide semiconductor layer are different from each other,
wherein the second oxide semiconductor layer covers and is in contact with a top surface and a side surface of the first oxide semiconductor layer,
wherein a region of the first oxide semiconductor layer and the second oxide semiconductor layer, which does not overlap with the gate electrode layer, contains a dopant,
wherein energy at a bottom of a conduction band of the first oxide semiconductor layer and energy at a bottom of a conduction band of the second oxide semiconductor layer are different from each other, and
wherein the bottom of the conduction band of the first oxide semiconductor layer and the bottom of the conduction band of the second oxide semiconductor layer are continuously connected in an energy band diagram.

17. The semiconductor device according to claim 16 , wherein the first oxide semiconductor layer comprises a crystal including a c-axis alignment.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei

Classifications

• H10D30/504

  wherein the stacked channels have different properties · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/78603

  Electricity · mapped topic

• H01L29/7782

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic