Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9698231-B2
Application number	US-201615015116-A
Country	US
Kind code	B2
Filing date	Feb 3, 2016
Priority date	Mar 31, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a tunnel insulation pattern on the substrate;
a charge storage pattern on the tunnel insulation pattern, the charge storage pattern comprising a width in a direction that is substantially perpendicular from a direction of the charge storage pattern to the substrate;
a dielectric pattern on the charge storage pattern, the dielectric pattern comprising a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, the width of the dielectric pattern being less than a width of the charge storage pattern;
a control gate on the dielectric pattern, the control gate comprising a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, the width of the control gate being greater than the width of the dielectric pattern;
a metal-containing gate on the control gate; and
a capping layer being on a sidewall of the metal-containing gate and extending from a sidewall of the control gate, the capping layer comprising a conductive material.

2. The semiconductor device of claim 1 , wherein the capping layer comprises a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, and the metal-containing gate comprises a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, and
wherein a sum of the width of the capping layer and the width of the metal-containing gate is greater than the width of the control gate.

3. The semiconductor device of claim 1 , wherein the capping layer comprises a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, and the metal-containing gate comprises a width in the direction that is substantially perpendicular from the direction of the charge storage pattern to the substrate, and
wherein a sum of the width of the capping layer and the width of the metal-containing gate is substantially the same as the width of the control gate.

4. The semiconductor device of claim 1 , wherein the capping layer is on substantially only the side wall of the metal-containing gate.

5. The semiconductor device of claim 1 , further comprising a buffer pattern between the metal-containing gate and the control gate,
wherein the capping layer covers substantially only sidewalls of the metal-containing gate and the buffer pattern.

6. The semiconductor device of claim 5 , wherein the buffer pattern comprises a metal nitride.

7. The semiconductor device of claim 1 , wherein the capping layer comprises polysilicon doped with impurities or amorphous silicon doped with impurities.

8. The semiconductor device of claim 7 , wherein the charge storage pattern and the control gate comprise polysilicon.

9. The semiconductor device of claim 8 , further comprising a gate mask on the metal-containing gate,
wherein the capping layer extends from substantially only the sidewall of the control gate to substantially only the sidewall of the metal-containing gate.

10. The semiconductor device of claim 1 , wherein a plurality of gate structures are arranged on the substrate, each of the gate structures comprising the tunnel insulation pattern, the charge storage pattern, the dielectric pattern, the control gate and the metal-containing gate.

11. The semiconductor device of claim 10 , wherein the tunnel insulation pattern comprises a protrusion on which the charge storage pattern is disposed, and
wherein the tunnel insulation pattern is commonly provided for the plurality of the gate structures.

12. The semiconductor device of claim 11 , wherein each protrusion comprises a width in the direction that is substantially perpendicular from the direction of the charge storage pattern from the substrate, and
wherein the width of each protrusion is less than the width of the charge storage pattern.

Assignees

• Namkoong Hyun
• Kim Dong-Kyum
• Kim Jung-Hwan
• Jee Jung Geun
• YANG Han-Vit
• Yoo Ji-Man
• Samsung Electronics Co Ltd

Inventors

• Namkoong Hyun
• Kim Dong-Kyum
• Kim Jung-Hwan
• Jee Jung Geun
• YANG Han-Vit
• Yoo Ji-Man

Classifications

• H01L29/42328 Primary

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic

• H01L29/42324

  Electricity · mapped topic