Power semiconductor device with improved stability and method for producing the same

Patent metadata

Field	Value
Publication number	US-9698138-B2
Application number	US-201514967578-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Dec 15, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A power semiconductor device includes a first contact, a second contact, and a semiconductor volume disposed between the first contact and the second contact. The semiconductor volume includes an n-doped field stop layer configured to spatially delimit an electric field that in the semiconductor volume during operation of the power semiconductor device, a heavily p-doped zone and a neighboring heavily n-doped zone, which together form a tunnel diode. The tunnel diode is located in the vicinity of, or adjacent to, or within the field stop layer. The tunnel diode is configured to provide protection against damage to the device due to a rise of an electron flow in an abnormal operating condition, by the fast provision of holes. Further, a method for producing such devices is provided.

First claim

What is claimed is:

1. A power semiconductor device, comprising:
a first contact;
a second contact;
a semiconductor volume disposed between the first contact and the second contact, including:
an n-doped field stop layer configured to spatially delimit an electric field formed in the semiconductor volume during operation of the power semiconductor device;
a heavily p-doped zone and a neighboring heavily n-doped zone, which together Form a tunnel diode, the tunnel diode being located in the vicinity of, or adjacent to, or within the field stop layer,
wherein the tunnel diode is configured to provide protection against damage to the device due to a rise of an electron flow in an abnormal operating condition, by the last provision of holes,
wherein a thickness of the heavily n-doped zone in a direction of a load current is at least 0.2 μm, and a thickness of the heavily p-doped zone in a direction of a load current is at least 0.1 μm.

2. The power semiconductor device of claim 1 , wherein a dopant concentration of the heavily p-doped zone is at least about 5×10 18 cm −3 , and a dopant concentration of the heavily n-doped zone is at least about 1×10 20 cm −3 .

3. The power semiconductor device of claim 1 , wherein one of the heavily n-doped zone and the heavily p-doped zone take up a fraction of the lateral cross sectional area of the power semiconductor device only, such that during operation a part of a load current flows in parallel to the tunnel diode through the remainder oldie cross sectional area.

4. The power semiconductor device of claim 3 , wherein the cross sectional area in the plane of the tunnel diode, which is not part of the tunnel diode, has a diameter of 15 μm or smaller.

5. The power semiconductor device of claim 1 , wherein at least one of the heavily p-doped zone and the heavily n-doped zone comprises a plurality of heavily doped islands.

6. The power semiconductor device of claim 1 , further comprising heavily p-doped islands, which together form the heavily p-doped zone and are embedded in the n-doped field stop layer.

7. The power semiconductor device of claim 1 , further comprising heavily n-doped islands, which together form the heavily n-doped zone and are embedded in the heavily p-doped zone.

8. The power semiconductor device of claim 1 , wherein the power semiconductor device is a diode, an IGBT, or as MOSFET.

9. A method for forming a power semiconductor device, the method comprising:
providing an n-doped semiconductor substrate;
providing at least one pn-junction in the substrate;
providing an n-doped held stop layer;
providing a heavily p-doped zone adjacent to the field stop layer; and
providing a heavily n-doped zone at least partially in contact with the heavily p-doped zone,
wherein the heavily p-doped zone and the heavily n-doped zone form a tunnel diode located in the vicinity of, or adjacent to, or within the field stop layer,
wherein a thickness of the heavily n-doped zone in a direction of a load current flow is at least 0.2 μm, and a thickness of the heavily p-doped zone in a direction of a load current flow is at least 0.1 μm.

10. The method of claim 9 , wherein a dopant concentration of the heavily p-doped zone is at least about 5×10 18 cm −3 , and a dopant concentration of the heavily n-doped zone is at least about 1×10 20 cm −3 .

11. The method of claim 9 , wherein the power semiconductor device is a diode, an IGBT, or as MOSFET.

12. The method or claim 9 , wherein at least one or the heavily p-doped zone and the heavily n-doped zone are provided in a form of a plurality of heavily doped islands.

13. The method or claim 9 , wherein either:
providing heavily p-doped islands, which together form the heavily p-doped zone and are embedded in the n-doped field stop layer;
providing heavily n-doped islands, which together form the heavily n-doped zone and are embedded in the heavily p-doped zone.

14. The method of claim 9 , wherein the n-doped field stop layer, the heavily p-doped zone, and the heavily n-doped zone are epitaxially deposited on a substrate, followed by ion implantation employing a mask.

15. The method or claim 9 , wherein dopings of the heavily p-doped zone and/or the heavily n-doped zone are provided by ion implantation in combination with subsequent annealing.

16. A power semiconductor device, comprising:
a first contact;
a second contact;
a semiconductor volume disposed between the first contact and the second contact, including:
an n-doped field stop layer configured to spatially delimit an electric field formed in the semiconductor volume during operation of the power semiconductor device;
a heavily p-doped zone and a neighboring heavily n-doped zone, which together form a tunnel diode, the tunnel diode being located in the vicinity of, or adjacent to, or within the field stop layer,
wherein the tunnel diode is configured to provide protection against damage to the device clue to a rise of an electron flow in an abnormal operating condition, by the fast provision of holes,
wherein a dopant concentration of the heavily p-doped zone is at least about 5×10 18 cm −3 , and a dopant concentration of the heavily n-doped zone is at least about 1×10 20 cm −3 .

17. A power semiconductor device, comprising:
a first contact;
a second contact;
a semiconductor volume disposed between the first contact and the second contact, including:
an n-doped field stop layer configured to spatially delimit an electric field formed in the semiconductor volume during operation of the power semiconductor device;
a heavily p-doped cone and a neighboring heavily n-doped zone, which together Corm a tunnel diode, the tunnel diode being located in the vicinity of, or adjacent to, or within the field stop layer,
wherein the tunnel diode is configured to provide protection against damage to the device due to a rise of an electron flow in an abnormal operating condition, by the fast provision holes,
wherein the n-doped field stop layer is directly adjacent a first side of the heavily p-doped zone and the heavily n-doped zone is directly adjacent a second side of the heavily p-doped zone opposite the first side.

18. The power semiconductor device of claim 17 , wherein the first side of the heavily p-doped zone faces the first contact, wherein the second side of the heavily p-doped zone faces the second contact, and wherein the heavily p-doped zone is separated from the second contact by the heavily n-doped zone.

Assignees

• Infineon Technologies Ag

Inventors

• Schulze Hans-Joachim
• Lutz Josef
• Pertermann Eric

Classifications

• H01L27/0255 Primary

  Electricity · mapped topic

• H01L29/66151

  Electricity · mapped topic

• H01L29/88

  Electricity · mapped topic

• H10D62/125

  Shapes of junctions between the regions · CPC title

• H10D8/80

  PNPN diodes, e.g. Shockley diodes or break-over diodes · CPC title