Metal deposition on substrates

US9698106B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9698106-B2
Application numberUS-201615073551-A
CountryUS
Kind codeB2
Filing dateMar 17, 2016
Priority dateMar 15, 2013
Publication dateJul 4, 2017
Grant dateJul 4, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: an isolation forming device configured to form an isolation layer over a substrate, the isolation forming device comprising a mask designed and arranged to limit the isolation layer to a peripheral region of the substrate; and a metal deposition station configured to deposit at least one metal layer over a side of the substrate. 2. The apparatus of claim 1 , wherein the isolation forming device comprises an isolation deposition station configured to deposit the isolation layer over the side of the substrate, and a lithography station configured to restrict the isolation layer to the peripheral region of the substrate. 3. The apparatus of claim 2 , wherein the lithography station is configured to coat the isolation layer with a photoresist, to partially expose the photoresist to light, to partially remove the photoresist, and to remove the isolation layer at places where the photoresist has been removed. 4. The apparatus of claim 1 , wherein the isolation forming device is configured to perform a plasma-enhanced chemical vapor deposition. 5. The apparatus of claim 1 , wherein the isolation forming device is configured to form at least one of an oxide or a nitride. 6. The apparatus of claim 1 , wherein the metal deposition station comprises an electroless plating device. 7. An apparatus comprising: an isolation forming device for forming an isolation layer over a semiconductor wafer, the isolation forming device comprising a mask designed and arranged to substantially limit the isolation layer to a peripheral region of the semiconductor wafer; and a metal deposition station for depositing at least one metal layer over a side of the semiconductor wafer, the metal layer being at least partially adjacent the isolation layer. 8. The apparatus of claim 7 , wherein the isolation forming device comprises an isolation deposition station for depositing the isolation layer over the side of the semiconductor wafer, and a lithography station configured to restrict the isolation layer to the peripheral region of the semiconductor wafer. 9. The apparatus of claim 8 , wherein the lithography station is configured to coat the isolation layer with a photoresist, to partially expose the photoresist to light, to partially remove the photoresist, and to remove the isolation layer at places where the photoresist has been removed. 10. The apparatus of claim 7 , wherein the isolation forming device is configured to perform a plasma-enhanced chemical vapor deposition. 11. The apparatus of claim 7 , wherein the isolation forming device is configured to form at least one of an oxide or a nitride. 12. The apparatus of claim 7 , wherein the metal deposition station comprises an electroless plating device.

Assignees

Inventors

Classifications

  • Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

  • Preparing SOI wafers · CPC title

  • by shaping · CPC title

  • comprising at least one plating chamber · CPC title

  • comprising at least one lithography chamber · CPC title

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Frequently asked questions

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What does patent US9698106B2 cover?
Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H10P50/73. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).