Integrated heat spreader that maximizes heat transfer from a multi-chip package

Patent metadata

Field	Value
Publication number	US-2016155682-A1
Application number	US-201615019931-A
Country	US
Kind code	A1
Filing date	Feb 9, 2016
Priority date	Jun 27, 2012
Publication date	Jun 2, 2016
Grant date	—

Abstract

In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.

First claim

What is claimed is:

1 . An electronic package, comprising:
a plurality of components on a substrate; a stiffener plate over the components, wherein the stiffener plate has openings to expose the components; and a plurality of individual integrated heat spreaders within the openings over the components.

2 . The electronic package of claim 1 , further comprising a first thermal interface material layer between the components and the individual integrated heat spreaders, wherein the first thermal interface material layer has a thickness which is minimized for the components.

3 . The electronic package of claim 1 , wherein the individual integrated heat spreaders are thicker over the components that are smaller in height.

4 . The electronic package of claim 1 , further comprising
a second thermal interface material layer on the individual integrated heat spreaders, wherein the second thermal interface material layer is thicker over the components that are smaller in height; and a heat sink on the second thermal interface material layer.

5 . The electronic package of claim 1 , wherein the components include a memory, a processor, a Graphics Processing Unit (GPU), a Platform Controller Hub (PCH), a Peripheral Component Interconnect (PCI), an on-chip system fabric, a network interface controller, a stacked component, a non-stacked component, a ball grid array (BGA) package, or any combination thereof.

6 . The electronic package of claim 1 , wherein the openings have a recess.

7 . A multi-chip package, comprising:
a substrate; a plurality of die components on the substrate; a first thermal interface material layer on the die components; and a plurality of individual integrated heat spreaders on the first thermal interface material layer, wherein the individual integrated heat spreaders are thicker over the die components that are smaller in height.

8 . The multi-chip package of claim 7 , further comprising:
a stiffener plate having openings over the die components, wherein the individual integrated heat spreaders are positioned within the openings.

9 . The multi-chip package of claim 7 , wherein the first thermal interface material layer has a thickness that is minimized for the die components.

10 . The multi-chip package of claim 7 , further comprising
a second thermal interface material layer on the individual integrated heat spreaders; and a heat sink on the second thermal interface material layer.

11 . The multi-chip package of claim 7 , wherein the die components include a memory, a processor, a Graphics Processing Unit (GPU), a Platform Controller Hub (PCH), a Peripheral Component Interconnect (PCI), on-chip system fabric, a network interface controller, a stacked component, a non-stacked component, a ball grid array (BGA) package, or any combination thereof.

12 . The multi-chip package of claim 7 , wherein the individual integrated heat spreaders have a step to attach to a stiffener plate over the die components.

13 . A method to manufacture an electronic package, comprising:
installing a stiffener plate over the components on a substrate, wherein the stiffener plate has openings; depositing a first thermal interface material layer on the components; and depositing a plurality of individual integrated heat spreaders within the openings on the first thermal interface layer.

14 . The method of claim 13 , wherein the individual integrated heat spreaders are thicker over the components which are smaller in height.

15 . The method of claim 13 , further comprising minimizing the first thermal interface material layer for the components.

16 . The method of claim 13 , further comprising
depositing a second thermal interface material layer on the individual integrated heat spreaders; and forming a heat sink on the second thermal interface material layer.

17 . The method of claim 13 , further comprising
forming the openings in the stiffener plate to expose the components.

18 . The method of claim 13 , wherein the depositing the plurality of individual integrated heat spreaders comprises
measuring a distance associated with a first one of the components; and selecting a first one of the individual integrated heat spreaders for the first one of the components based on the measured distance.

19 . The method of claim 13 , further comprising
forming recesses within the openings; forming steps on the individual integrated heat spreaders; and placing the steps on the recesses.

20 . The method of claim 13 , further comprising baking the first thermal interface material to adhere to the components and the individual integrated heat spreaders.

21 . The method of claim 13 , wherein the components include a memory, a processor, a Graphics Processing Unit (GPU), a Platform Controller Hub (PCH), a Peripheral Component Interconnect (PCI), on-chip system fabric, a network interface controller, or any combination thereof.

Assignees

• Intel Corp

Inventors

• Ahuja Sandeep
• Buddrius Eric W
• Flynn Roger D
• Agarwal Rajat

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/00

  Package configurations · CPC title