Semiconductor device and semiconductor module

Patent metadata

Field	Value
Publication number	US-9697948-B2
Application number	US-201414537234-A
Country	US
Kind code	B2
Filing date	Nov 10, 2014
Priority date	Nov 13, 2013
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

First claim

What is claimed is:

1. A semiconductor device comprising:
an insulating layer;
a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in a vertical direction;
a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in plan view and is connected with potential lower than the high voltage coil, the low potential portion including
a low voltage pad which is exposed to a surface of the insulating layer, and
low voltage wiring which is connected between the low voltage coil and the low voltage pad, the low voltage wiring including a lead-out wiring formed in a linear shape, the lead-out wiring being led out from the low voltage coil at a position lower than a position of the low voltage coil in the vertical direction to a region under the low voltage pad; and

an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member, the electrically floated metal member being arranged away from the high voltage region in a horizontal direction and between the high voltage coil and the low voltage pad, and crossing the lead-out wiring in plan view.

2. The semiconductor device according to claim 1 , wherein the electric field shield portion includes a capacitor composed of a plurality of electrode plates which face each other at intervals in a horizontal direction.

3. The semiconductor device according to claim 2 , wherein three or more electrode plates are provided at equal intervals.

4. The semiconductor device according to claim 2 , wherein three or more electrode plates are provided at unequal intervals.

5. The semiconductor device according to claim 1 , wherein
the insulating layer includes an insulating film laminated structure including a plurality of insulating films which are laminated successively,
the high voltage coil and the low voltage coil are respectively embedded in separate insulating films,
one or more insulating films are interposed between the high voltage coil and the low voltage coil, and
the electric field shield portion includes electrode plates which are embedded in at least one insulating film.

6. The semiconductor device according to claim 5 , wherein a plurality of electrode plates face the same insulating layer at intervals and constitute a capacitor.

7. The semiconductor device according to claim 6 , wherein three or more electrode plates are provided at equal intervals.

8. The semiconductor device according to claim 6 , wherein three or more electrode plates are provided at unequal intervals.

9. The semiconductor device according to claim 5 , wherein the electrode plates are provided in the same insulating layer independently so as not to overlap each other in a horizontal direction.

10. The semiconductor device according to claim 5 , wherein the electrode plates are embedded in an insulating film for the high voltage coil, an insulating film for the low voltage coil, and an insulating film disposed therebetween.

11. The semiconductor device according to claim 10 , wherein the electrode plates embedded in the respective insulating films are arranged continuously in a vertical direction.

12. The semiconductor device according to claim 5 , wherein the electrode plates are embedded selectively in an insulating film for the high voltage coil and an insulating film for the low voltage coil.

13. The semiconductor device according to claim 5 , wherein
the low potential portion includes a shield field layer which is embedded in a plurality of insulating films so as to surround the high voltage region, and
the electrode plates are embedded in the same insulating film as the shield layer.

14. The semiconductor device according to claim 5 , wherein
the high voltage coil is an upper coil which is disposed at a side relatively near to a surface of the insulating film laminated structure and the low voltage coil is a lower coil which is disposed below the upper coil, and
the low potential portion includes low voltage wiring which is connected with the lower coil and penetrates the insulating film laminated structure in a lamination direction.

15. The semiconductor device according to claim 14 , wherein the low potential portion includes a low voltage pad which is exposed to a surface of the insulating layer laminated structure and is connected with the low voltage wiring.

16. The semiconductor device according to claim 1 , wherein a distance L 1 between the high voltage coil and the electric field shield portion in a horizontal direction is larger than a distance L 2 between the high voltage coil and the low voltage coil in a vertical direction.

17. The semiconductor device according to claim 1 , wherein the electric field shield portion surrounds the high voltage coil.

18. The semiconductor device according to claim 1 , further comprising a substrate arranged to support the insulating layers,
wherein the low voltage coil is connected with the substrate.

19. A semiconductor module comprising:
a semiconductor device including:
an insulating layer;
a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in a vertical direction;
a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in plan view and is connected with potential lower than the high voltage coil, the low potential portion including
a low voltage pad which is exposed to a surface of the insulating layer, and
low voltage wiring which is connected between the low voltage coil and the low voltage pad, the low voltage wiring including a lead-out wiring formed in a linear shape, the lead-out wiring being led out from the low voltage coil at a position lower than a position of the low voltage coil in the vertical direction to a region under the low voltage pad; and

an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member, the electrically floated metal member being arranged away from the high voltage region in a horizontal direction and between the high voltage coil and the low voltage pad, and crossing the lead-out wiring in plan view;

a low voltage element which is electrically connected with the low voltage coil of the semiconductor device;
a high voltage element which is electrically connected with the high voltage coil of the semiconductor device; and
a resin package arranged to collectively seal the semiconductor device, the low voltage element and the high voltage element.

20. A semiconductor device, comprising:
an insulating layer including a first portion and a second portion that are disposed at an interval in a vertical direction, the insulating layer including first and second regions in a horizontal direction, the second region including a portion surrounding the first region in plan view, the second region including a low potential area, the low potential area including
a low voltage pad which is exposed to a surface of the insulating layer, and
low voltage wiring which is connected between the low voltage coil and the low voltage pad, the low voltage wiring including a lead-out wiring formed in a linear shape, the lead-out wiring being led out from the low voltage coil at a position lower than a position of the low voltage coil in the vertical direction to a region under the low voltag

Assignees

• Rohm Co Ltd

Inventors

• Osada Kosei
• Nishimura Isamu
• Kagawa Tetsuya
• Yanagishima Daiki
• Ishikawa Toshiyuki
• Mifuji Michihiko
• Kageyama Satoshi
• Kasahara Nobuyuki

Classifications

• H10W90/759

  between a chip and a laterally-adjacent discrete passive device · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title