Magnetic-core three-dimensional (3D) inductors and packaging integration

Patent metadata

Field	Value
Publication number	US-9693461-B2
Application number	US-201514684256-A
Country	US
Kind code	B2
Filing date	Apr 10, 2015
Priority date	Apr 16, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.

First claim

What is claimed is:

1. A 3-dimensinal (3-D) magnetic core device, the device comprising:
a substrate;
a first magnetic shell formed on the substrate;
a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell;
a magnetic core plane formed on the first insulator layer;
a second group of conductive traces embedded in a second insulator layer formed on the magnetic core plane; and
a second magnetic shell formed on the second insulator layer,
wherein the first and second group of conductive traces are conductively coupled by using conductive vias, and wherein the first and second magnetic shells and the magnetic core plane are magnetically coupled by using magnetic vias.

2. The device of claim 1 , wherein the first and second group of conductive traces comprise horizontal parallel conductive traces, and wherein the horizontal parallel conductive traces comprise copper traces.

3. The device of claim 2 , wherein the conductive vias are configured to form a first helical coil around the magnetic core plane.

4. The device of claim 1 , wherein the magnetic core plane comprises a laminated magnetic core, and wherein the magnetic core plane is slotted into a plurality of strips to reduce eddy current.

5. The device of claim 1 , wherein the first and second group of conductive traces and the conductive vias form a primary coil of a transformer, and wherein a secondary coil of the transformer is structurally similar to the primary coil.

6. The device of claim 5 , wherein counts of turns of the primary and secondary coils are different, and wherein the primary and secondary coils are formed side-by-side.

7. The device of claim 6 , wherein the first and second group of conductive traces of the secondary coil are formed in a same plane so that magnetic fields generated by the first and second coils are substantially perpendicular to one another.

8. The device of claim 1 , wherein input/output (IO) contact pads are positioned on more than one surface of the device, wherein the IO contact pads are positioned on opposite surfaces of the device, wherein the IO contact pads are positioned on any of multiple surfaces of the device.

9. The device of claim 1 , wherein the device is integrated in an interposer having a two-dimensional (2D) array of input/output (IO) connections, wherein the interposer includes a high-density die-to-die interconnection bus for coupling to a plurality of chips, and wherein the device further comprises one or more 3-D capacitors coupled to the 3-D magnetic core device.

10. The device of claim 1 , wherein:
the device is integrated in a passive device package (PDP),
the device is integrated with one or more capacitors in the PDP,
the PDP comprises a surface-mount (SMT) PDP,
the PDP comprises a ball grid array BGA or a land grid array (LGA) PDP,
the PDP comprises electrical interconnect contacts on at least one of a top surface or a sidewall of the PDP, and
two or more PDPs are coupled by at least one of surface mounting on top of one another or by side-by-side interconnection.

11. The device of claim 1 , wherein the device is integrated in one of following configurations:
the device is integrated in a core of an integrated circuit (IC) packaging substrate and is coupled to an active chip through metal layers on top of the core of the IC packaging;
the device is mounted on an IC packaging substrate and coupled to an active chip mounted on the IC packaging substrate;
the device is integrated on a top of an active chip mounted on a an IC packaging substrate and is coupled to an active portion of the active chip through vias; or
the device is integrated in an interposer coupled to an IC packaging substrate and an active chip is mounted over the interposer and is coupled to the IC packaging substrate using vias passing through the interposer.

12. A method for providing a 3-dimensinal (3-D) magnetic core device, the method comprising:
providing a substrate;
forming a first magnetic shell on the substrate;
forming, on the first magnetic shell, a first group of conductive traces embedded in a first insulator layer;
forming a magnetic core plane on the first insulator layer;
forming, on the magnetic core plane, a second group of conductive traces embedded in a second insulator layer;
forming a second magnetic shell on the second insulator layer; and
magnetically coupling the first and second magnetic shells and the magnetic core plane by using magnetic vias.

13. The method of claim 12 , further comprising conductively coupling the first and second group of conductive traces by using conductive vias, wherein forming the first and second group of conductive traces comprises forming horizontal parallel conductive traces, and wherein forming the horizontal parallel conductive traces comprises forming copper traces.

14. The method of claim 13 , further comprising configuring the conductive vias to form a first helical coil around the magnetic core plane.

15. The method of claim 12 , wherein the magnetic core plane comprises a laminated magnetic core, and wherein the method further comprises slotting the magnetic core plane into a plurality of strips to reduce eddy current.

16. The method of claim 12 , further comprising:
forming a primary coil of a transformer by using the first and second group of conductive traces and the conductive vias, and
forming a secondary coil of the transformer structurally similar to the primary coil.

17. The method of claim 16 , wherein counts of turns of the primary and secondary coils are different, and the method further comprises forming the primary and secondary coils side-by-side.

18. The method of claim 17 , further comprising forming the first and second group of conductive traces of the secondary coil in a same plane so that magnetic fields generated by the first and second coils are substantially perpendicular to one another.

19. The method of claim 12 , further comprising:
positioning input/output (IO) contact pads on more than one surface of the device,
positioning the IO contact pads on opposite surfaces of the device, and
positioning the IO contact pads on any of multiple surfaces of the device.

20. The method of claim 12 , further comprising integrating the 3-D magnetic core device in an interposer having a two-dimensional (2D) array of input/output (IO) connections, and coupling one or more 3-D capacitors to the 3-D magnetic core device, wherein the interposer includes a high-density die-to-die interconnection bus for coupling to a plurality of chips.

21. The method of claim 12 , further comprising integrating the 3-D magnetic core device in a passive device package (PDP), wherein:
the 3-D magnetic core device is integrated with one or more capacitors in the PDP,
the PDP comprises a surface-mount (SMT) PDP,
the PDP comprises a ball grid array BGA or a land grid array (LGA) PDP,
the PDP comprises electrical interconnect contacts on at least one of a top surface or a sidewall of the PDP, and
the method further comprises coupling two or more PDPs by at least one of surface mounting on top of one another or by side-by-side interconnection.

22. The method of claim 12 , further comprising one of:
integrating the 3-D magnetic core device in a core of an integrated circuit (IC) packaging substrate and coupling the 3-D magnetic core device to an active chip through metal layers on top of the core of the IC packaging;
mounting the 3-D magnetic core device

Assignees

• Broadcom Corp
• Avago Technologies General Ip

Inventors

• Zhao Sam Ziqun
• Law Edward
• Karikalan Sampath Komarapalayam
• Kistler Neal Andrew
• Khan Rezaur Rahman
• Vorenkamp Pieter

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H01F41/046

  structurally combined with ferromagnetic material · CPC title

• H01F17/0013 Primary

  with stacked layers · CPC title

• H01F17/045

  with core of cylindric geometry and coil wound along its longitudinal axis, i.e. rod or drum core · CPC title