Three-dimensional semiconductor transistor with gate contact in active region

Patent metadata

Field	Value
Publication number	US-9691897-B2
Application number	US-201514867193-A
Country	US
Kind code	B2
Filing date	Sep 28, 2015
Priority date	Sep 28, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.

First claim

The invention claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate and at least one fin coupled thereto and having an active area with a source, a drain and a gate encompassing a portion of the at least one fin;
a trench silicide contact for each of the source and drain and a gate contact, a top portion of each contact situated at a same level in the active area; and
wherein a portion of each trench silicide contact is partially located below a bottom surface of the gate contact.

2. The semiconductor structure of claim 1 , wherein each trench silicide contact comprises silicide and at least one conductive metal.

3. A three-dimensional semiconductor transistor, comprising:
a semiconductor substrate;
a fin coupled to the substrate, the fin comprising an active region across a top portion thereof, the active region comprising a source, a drain and a channel region therebetween;
a gate situated above the channel region;
a gate contact situated in the active region, wherein a top portion of the gate contact is at a same level as a top portion of a source contact and a drain contact; and
wherein each of the source contact and the drain contact has a portion thereof located below the gate contact while electrical contact is maintained between an entirety of a top surface of each of the source and the drain, and the source contact and the drain contact, respectively.

4. The three-dimensional transistor of claim 3 , wherein the source contact and the drain contact each have a roughly L-shaped portion in direct contact with the source and the drain.

5. The three-dimensional transistor of claim 3 , wherein the semiconductor substrate comprises a bulk semiconductor substrate with a plurality of the fins coupled thereto.

Assignees

• Globalfoundries Inc

Inventors

• Xie Ruilong
• Labonte Andre
• Knorr Andreas

Classifications

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40 Primary

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title