Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators

Patent metadata

Field	Value
Publication number	US-9691860-B2
Application number	US-201514698817-A
Country	US
Kind code	B2
Filing date	Apr 28, 2015
Priority date	May 2, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A strain-relieved buffer is formed by forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate. The first SiGe layer is patterned to form at least two SiGe structures so there is a space between the SiGe structures. An oxide is formed on the SiGe structures, and the SiGe structures are mesa annealed. The oxide is removed to expose a top portion of the SiGe structures. A second SiGe layer is formed on the exposed portion of the SiGe structures so that the second SiGe layer covers the space between the SiGe structures, and so that a percentage Ge content of the first and second SiGe layers are substantially equal. The space between the SiGe structures is related to the sizes of the structures adjacent to the space and an amount of stress relief that is associated with the structures.

First claim

What is claimed is:

1. A method to form a strain-relieved buffer (SRB), the method comprising:
forming a first silicon-germanium (SiGe) layer directly on a surface of a bulk silicon (Si) substrate;
patterning the first SiGe layer to form at least two SiGe structures so there is a space between the at least two SiGe structures;
forming an oxide on the at least two SiGe structures;
mesa annealing the at least two SiGe structures;
removing a portion of the oxide to expose a top portion of the at least two SiGe structures; and
forming a second SiGe layer on the exposed top portion of the at least two SiGe structures, the second SiGe layer covering the space between the at least two SiGe structures.

2. The method according to claim 1 , wherein forming the first SiGe layer comprises forming the first SiGe layer by epitaxial deposition, and
wherein forming the second SiGe layer comprises forming the second SiGe layer by epitaxial deposition.

3. The method according to claim 2 , wherein a percentage Ge content of the first SiGe layer is substantially equal to a percentage Ge content of the second SiGe layer.

4. The method according to claim 3 , wherein the percentage Ge content of the second SiGe layer is greater than 30%.

5. The method according to claim 4 , wherein a threading dislocation (TD) density (TDD) of the second SiGe layer is less than 1×10 5 TD/cm 2 .

6. The method according to claim 3 , wherein patterning the first SiGe layer comprises patterning the first SiGe layer so that each SiGe structure comprises a length and a width in a direction along the surface of the bulk Si substrate, the space between each SiGe structure comprising a predetermined distance between each SiGe structure, and the predetermined distance being related to the length and the width of the SiGe structures adjacent to the space and an amount of stress relief that is associated with each SiGe structure.

7. The method according to claim 1 , wherein the SRB is part of a System on a Chip (SOC).

8. The method according to claim 7 , wherein the SOC is part of an electronic device comprising a touch-screen display.

9. A method to form a strain-relieved buffer (SRB), the method comprising:
forming a first silicon-germanium (SiGe) layer on a surface of a substrate;
patterning the first SiGe layer to form at least two SiGe structures so there is a space between the at least two SiGe structures, each SiGe structure comprising a length and a width in a direction along the surface of the substrate, the space between each SiGe structure comprising a predetermined distance between each SiGe structure, and the predetermined distance being related to the length and the width of the SiGe structures adjacent to the space and an amount of stress relief that is associated with each SiGe structure;
forming an oxide on the at least two SiGe structures;
mesa annealing the at least two SiGe structures;
removing a portion of the oxide to expose a top portion of the at least two SiGe structures; and
forming a second SiGe layer on the exposed top portion of the at least two SiGe structures, the second SiGe layer covering the space between the at least two SiGe structures.

10. The method according to claim 9 , wherein the substrate is a bulk silicon (Si) substrate, and
wherein the first silicon-germanium (SiGe) layer is formed directly on the surface of the bulk Si substrate.

11. The method according to claim 9 , wherein forming the first SiGe layer comprises forming the first SiGe layer by epitaxial deposition, and
wherein forming the second SiGe layer comprises forming the second SiGe layer by epitaxial deposition.

12. The method according to claim 11 , wherein a percentage Ge content of the first SiGe layer is substantially equal to a percentage Ge content of the second SiGe layer.

13. The method according to claim 12 , wherein the percentage Ge content of the second SiGe layer is greater than 30%, and
wherein a threading dislocation (TD) density (TDD) of the second SiGe layer is less than 1×10 5 TD/cm 2 .

14. The method according to claim 12 , wherein the SRB is part of a System on a Chip (SOC), and
wherein the SOC is part of an electronic device comprising a touch-screen display.

15. A method to form a strain-relieved buffer (SRB), the method comprising:
forming a first silicon-germanium (SiGe) layer on a surface of a substrate;
patterning the first SiGe layer to form at least two SiGe structures so there is a space between the at least two SiGe structures;
forming an oxide on the at least two SiGe structures;
mesa annealing the at least two SiGe structures;
removing a portion of the oxide to expose a top portion of the at least two SiGe structures; and
forming a second SiGe layer on the exposed top portion of the at least two SiGe structures, the second SiGe layer covering the space between the at least two SiGe structures, and a percentage Ge content of the first SiGe layer being substantially equal to a percentage Ge content of the second SiGe layer.

16. The method according to claim 15 , wherein the substrate is a bulk silicon (Si) substrate, and
wherein the first silicon-germanium (SiGe) layer is formed directly on the surface of the bulk Si substrate.

17. The method according to claim 16 , wherein each SiGe structure comprising a length and a width in a direction along the surface of the substrate, the space between each SiGe structure comprising a predetermined distance between each SiGe structure, and the predetermined distance being related to the length and the width of the SiGe structures adjacent to the space and an amount of stress relief that is associated with each SiGe structure.

18. The method according to claim 15 , wherein forming the first SiGe layer comprises forming the first SiGe layer by epitaxial deposition, and
wherein forming the second SiGe layer comprises forming the second SiGe layer by epitaxial deposition.

19. The method according to claim 15 , wherein the percentage Ge content of the second SiGe layer is greater than 30%, and
wherein a threading dislocation (TD) density (TDD) of the second SiGe layer is less than 1×10 5 TD/cm 2 .

20. The method according to claim 15 , wherein the SRB is part of a System on a Chip (SOC), and
wherein the SOC is part of an electronic device comprising a touch-screen display.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei-E
• Rodder Mark S
• Sengupta Rwik

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/278

  Pendeoepitaxy · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title