Cylindrical embedded capacitors

Patent metadata

Field	Value
Publication number	US-9691840-B2
Application number	US-201314132563-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Sep 1, 2010
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

First claim

What is claimed is:

1. A method comprising:
forming a first opening in a first region of a substrate, wherein the first opening extends from a front surface of the substrate into the substrate;
forming a second opening in a second region of the substrate, wherein the second opening extends from the front surface into the substrate;
forming a first conductive layer to fully fill the first opening and partially fill a portion of the second opening;
forming a first insulation layer over the first conductive layer;
forming a second conductive layer over the first insulation layer;
performing a planarization process to remove excess portions of the first conductive layer, the first insulation layer, and the second conductive layer, wherein the excess portions are outside the first opening and the second opening;
forming a second insulation layer over the second conductive layer;
forming a third conductive layer over the second insulation layer, wherein the second insulation layer and the third conductive layer are filled into the second opening; and
after the third conductive layer is formed, grinding a back surface of the substrate to expose the first conductive layer, the first insulation layer and the second conductive layer, wherein the first conductive layer, the first insulation layer, and the second conductive layer form a capacitor in the second opening, and the first conductive layer forms a through-substrate via (TSV) in the first opening.

2. The method of claim 1 , wherein the second opening has a second lateral dimension greater than a first lateral dimension of the first opening.

3. The method of claim 1 , wherein the second opening has a second depth greater than a first depth of the first opening.

4. The method of claim 1 , wherein the substrate is a semiconductor substrate, and the first opening and the second opening extend into the semiconductor substrate.

5. The method of claim 1 further comprising, before the step of forming the first conductive layer, forming an isolation layer in the first opening and the second opening.

6. The method of claim 5 , wherein the isolation layer is a dielectric layer.

7. The method of claim 1 , further comprising forming a metal bump over the front surface of the substrate, wherein the metal bump is electrically coupled to at least one of the capacitor and the TSV.

8. The method of claim 1 , further comprising forming a metal bump underlying substrate, wherein the metal bump is electrically coupled to the TSV.

9. A method comprising:
etching a semiconductor substrate to form a first opening and a second opening, wherein the first opening has a first lateral dimension smaller than a second lateral dimension of the second opening;
forming an isolation layer in the first opening and the second opening simultaneously;
forming a first conductive layer to fill in the first opening and the second opening simultaneously, with the first conductive layer being over the isolation layer, wherein the isolation layer and the first conductive layer fill an entirety of the first opening, and a part of the second opening;
forming a first insulation layer over the first conductive layer, wherein the first insulation layer is filled into the second opening;
forming a second conductive layer over the first insulation layer, wherein the second conductive layer is filled into the second opening;
performing a planarization to remove excess portions of the isolation layer, the first conductive layer, the first insulation layer, and the second conductive layer, wherein the excess portions are over a top surface of the semiconductor substrate; and
forming electrical connections to connect to a first portion of the first conductive layer and a second portion of the second conductive layer to form a capacitor, with the first portion and the second portion being in the second opening, wherein the electrical connections comprise solder bumps.

10. The method of claim 9 further comprising forming a dielectric layer underlying and in contact with bottom ends of the first portion and the second portion.

11. The method of claim 9 further comprising forming additional electrical connections to connect to opposite ends of a portion of the first conductive layer, wherein the portion of the first conductive layer is in the first opening.

12. The method of claim 11 , wherein the electrical connections comprise solder bumps.

13. The method of claim 9 further comprising:
forming a second insulation layer over the second conductive layer, wherein the second insulation layer is filled into the second opening; and
forming a third conductive layer over the second insulation layer, wherein the third conductive layer is filled into the second opening.

14. The method of claim 9 , wherein the first insulation layer and the second conductive layer are formed in the region directly over the first opening.

15. The method of claim 9 further comprising performing a backside grinding from a backside of the semiconductor substrate, wherein after the backside grinding, a bottom surface and a first portion and a second portion of the first conductive layer in the first opening and the second opening, respectively, are exposed.

16. The method of claim 9 , wherein the isolation layer is a dielectric layer.

17. A method comprising:
etching a semiconductor substrate to form a first opening and a second opening, wherein the first opening has a first lateral dimension smaller than a second lateral dimension of the second opening, and wherein the first opening has a first depth smaller than a second depth of the second opening;
forming dielectric isolation layer, with the dielectric isolation layer comprising a first portion in the first opening and a second portion in the second opening;
forming a first conductive layer over the dielectric isolation layer, with the first conductive layer comprising:
a first portion in the first opening, wherein the first opening is fully filled by the first portion of the first conductive layer and the first portion of the dielectric isolation layer; and
a second portion filling a part of the second opening;

forming an insulation layer over the first conductive layer, wherein the insulation layer is filled into the second opening;
forming a second conductive layer over the insulation layer, wherein the second conductive layer comprises a portion filled into the second opening;
forming first electrical connections to connect to opposite ends of the first portion of the first conductive layer to form a through-substrate via; and
forming second electrical connections to connect to a top end of the second portion of the first conductive layer and a top end of the portion of the second conductive layer in the second opening to form a capacitor.

18. The method of claim 17 further comprising, after forming the second conductive layer, performing a planarization to expose a top surface of the semiconductor substrate, wherein the second electrical connections are formed after the planarization.

19. The method of claim 17 further comprising, after forming the second conductive layer, performing a backside grinding to expose a bottom end of the first portion of the first conductive layer, wherein the first electrical connections are formed after the backside grinding.

20. The method of claim 17 , wherein the first electrical connections and the second electrical connections comprise solder bumps.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su An-Jhih
• Hsieh Chi-Chun
• Wang Tzu-Yu
• Wu Wei-Cheng
• Hu Hsien-Pin
• Hou Shang-Yun
• Chiou Wen-Chih
• Jeng Shin-Puu

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9223

  with redistribution layers [RDL] · CPC title