Magnetic memory devices

Patent metadata

Field	Value
Publication number	US-9691816-B2
Application number	US-201514964251-A
Country	US
Kind code	B2
Filing date	Dec 9, 2015
Priority date	Jan 22, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure.

First claim

What is claimed is:

1. A magnetic memory device, comprising:
a lower insulating layer on a substrate;
an insulating structure on the lower insulating layer;
a lower contact in the lower insulating layer;
a lower electrode in the insulating structure and electrically connected to the lower contact; and
a magnetic tunnel junction pattern in contact with at least a portion of a top surface of the insulating structure and at least a portion of a top surface of the lower electrode,
wherein the lower electrode comprises a bottom portion and a protruding portion protruding from a top surface of the bottom portion toward the magnetic tunnel junction pattern,
wherein at least a portion of the top surface of the bottom portion of the lower electrode is in contact with the insulating structure, and
wherein a root-mean-square roughness of the top surfaces of the insulating structure and the lower electrode that are in contact with the magnetic tunnel junction pattern ranges from 0.01 nanometers (nm) to 1 nm.

2. The device of claim 1 , wherein a first contact area between the magnetic tunnel junction pattern and the top surface of the insulating structure is larger than a second contact area between the magnetic tunnel junction pattern and the top surface of the lower electrode.

3. The device of claim 1 , wherein the bottom portion of the lower electrode is spaced apart from the magnetic tunnel junction pattern.

4. The device of claim 1 , wherein the insulating structure comprises an amorphous structure.

5. The device of claim 4 , wherein the lower electrode comprises a polycrystalline structure.

6. The device of claim 1 , wherein a first roughness of the top surface of the insulating structure is less rough than a second roughness of a top surface of the protruding portion of the lower electrode.

7. The device of claim 1 , wherein the protruding portion of the lower electrode comprises a top surface coplanar with the top surface of the insulating structure.

8. A magnetic memory device, comprising:
a lower insulating layer on a substrate;
a lower contact in the lower insulating layer;
a first insulating pattern on the lower insulating layer and comprising a gap overlying the lower contact;
a lower electrode in the gap, on the lower contact and on a side surface of the first insulating pattern;
a second insulating pattern in the gap, on the lower electrode; and
a magnetic tunnel junction pattern in contact with at least a portion of a top surface of each of the lower electrode, the first insulating pattern, and the second insulating pattern,
wherein a root-mean-square roughness of the top surfaces of the first and second insulating patterns and the lower electrode that are in contact with the magnetic tunnel junction pattern ranges from 0.01 nanometers (nm) to 1 nm.

9. The device of claim 8 ,
wherein the first and second insulating patterns define an insulating structure, and
wherein a first contact area between the magnetic tunnel junction pattern and a top surface of the insulating structure is larger than a second contact area between the magnetic tunnel junction pattern and the top surface of the lower electrode.

10. The device of claim 8 ,
wherein at least one of the first and second insulating patterns comprises an amorphous structure, and
wherein the lower electrode comprises a polycrystalline structure.

11. The device of claim 8 , wherein a roughness of the top surface of each of the first and second insulating patterns is less rough than a roughness of the top surface of the lower electrode.

12. The device of claim 8 , wherein the top surface of the lower electrode is coplanar with the top surfaces of the first and second insulating patterns.

13. The device of claim 8 , wherein the lower electrode comprises a closed-bottom hollow cylinder shape.

Assignees

• Han Shinhee
• Lee Kilho
• Song Yoonjong
• Samsung Electronics Co Ltd

Inventors

• Han Shinhee
• Lee Kilho
• Song Yoonjong

Classifications

• H01L43/02

  Electricity · mapped topic

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L27/222 Primary

  Electricity · mapped topic

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title