Semiconductor memory device including memory cell which includes transistor and capacitor

Patent metadata

Field	Value
Publication number	US-9691772-B2
Application number	US-201213402194-A
Country	US
Kind code	B2
Filing date	Feb 22, 2012
Priority date	Mar 3, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A semiconductor memory device includes a transistor and a capacitor. The transistor includes: an insulating film in which a groove portion is provided; a pair of electrodes separated so that the groove portion is sandwiched therebetween; an oxide semiconductor film which is in contact with the pair of electrodes and side surfaces and a bottom surface of the groove portion and has a thickness value smaller than a depth value of the groove portion; a gate insulating film covering the oxide semiconductor film; and a gate electrode provided to overlap with the oxide semiconductor film with the gate insulating film positioned therebetween.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell comprising a transistor and a capacitor,
wherein the transistor comprises:
a pair of electrodes over an insulating film including a groove portion;
an oxide semiconductor film in contact with the pair of electrodes and side surfaces of the groove portion, the oxide semiconductor film including a first depression portion overlapping with the groove portion;
a gate insulating film over the oxide semiconductor film; and
a gate electrode over the gate insulating film; and

wherein the capacitor comprises:
a dielectric film over one of the pair of electrodes; and
a conductive film over the dielectric film,

wherein the conductive film is formed from the same layer as the gate electrode,
wherein the dielectric film is provided in the same layer as the gate insulating film,
wherein the gate electrode of the transistor is electrically connected to a word line,
wherein the other of the pair of electrodes of the transistor is electrically connected to a bit line, and
wherein the oxide semiconductor film comprises a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the side surfaces of the groove portion.

2. The semiconductor memory device according to claim 1 , wherein the oxide semiconductor film is in contact with a bottom surface of the groove portion.

3. The semiconductor memory device according to claim 1 , wherein the side surfaces of the groove portion are coextensive with side surfaces of the pair of electrodes.

4. The semiconductor memory device according to claim 1 , wherein the gate electrode includes a second depression portion overlapping with the groove portion.

5. The semiconductor memory device according to claim 1 , wherein the conductive film of the capacitor is grounded.

6. A semiconductor memory device comprising:
a memory cell comprising a transistor and a capacitor,
wherein the transistor comprises:
a pair of electrodes over an insulating film including a groove portion;
an oxide semiconductor film in contact with the pair of electrodes and side surfaces of the groove portion, the oxide semiconductor film including a first depression portion overlapping with the groove portion;
a gate insulating film over the oxide semiconductor film; and
a gate electrode over the gate insulating film; and

wherein the capacitor comprises:
a dielectric film over one of the pair of electrodes; and
a conductive film over the dielectric film,

wherein the conductive film includes the same material as the gate electrode,
wherein the dielectric film includes the same material as the gate insulating film,
wherein the conductive film is formed from the same layer as the gate electrode,
wherein the dielectric film is provided in the same layer as the gate insulating film,
wherein the gate electrode of the transistor is electrically connected to a word line,
wherein the other of the pair of electrodes of the transistor is electrically connected to a bit line, and
wherein the oxide semiconductor film comprises a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the side surfaces of the groove portion.

7. The semiconductor memory device according to claim 6 , wherein the oxide semiconductor film is in contact with a bottom surface of the groove portion.

8. The semiconductor memory device according to claim 6 , wherein the side surfaces of the groove portion are coextensive with side surfaces of the pair of electrodes.

9. The semiconductor memory device according to claim 6 , wherein the gate electrode includes a second depression portion overlapping with the groove portion.

10. The semiconductor memory device according to claim 6 , wherein the conductive film of the capacitor is grounded.

11. A semiconductor memory device comprising:
a memory cell comprising a transistor and a capacitor,
wherein the transistor comprises:
a pair of electrodes over an insulating film including a groove portion;
an oxide semiconductor film in contact with the pair of electrodes and side surfaces of the groove portion, the oxide semiconductor film having a thickness value smaller than a depth value of the groove portion;
a gate insulating film over the oxide semiconductor film; and
a gate electrode over the gate insulating film; and

wherein the capacitor comprises:
a dielectric film over one of the pair of electrodes; and
a conductive film over the dielectric film,

wherein the conductive film includes the same material as the gate electrode,
wherein the dielectric film includes the same material as the gate insulating film,
wherein the conductive film is formed from the same layer as the gate electrode,
wherein the dielectric film is provided in the same layer as the gate insulating film,
wherein the gate electrode of the transistor is electrically connected to a word line,
wherein the other of the pair of electrodes of the transistor is electrically connected to a bit line, and
wherein the oxide semiconductor film comprises a crystal part whose c-axis is aligned in a direction parallel to a normal vector of the side surfaces of the groove portion.

12. The semiconductor memory device according to claim 11 , wherein the oxide semiconductor film is in contact with a bottom surface of the groove portion.

13. The semiconductor memory device according to claim 11 , wherein the oxide semiconductor film includes a first depression portion overlapping with the groove portion.

14. The semiconductor memory device according to claim 11 , wherein the gate electrode includes a second depression portion overlapping with the groove portion.

15. The semiconductor memory device according to claim 11 , wherein the conductive film of the capacitor is grounded.

Assignees

• Noda Kosei
• Endo Yuta
• Semiconductor Energy Lab

Inventors

• Noda Kosei
• Endo Yuta

Classifications

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426 Primary

  Oxides · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title