Dual thick EG oxide integration under aggressive SG fin pitch

Patent metadata

Field	Value
Publication number	US-9691664-B1
Application number	US-201615170126-A
Country	US
Kind code	B1
Filing date	Jun 1, 2016
Priority date	Jun 1, 2016
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A method of forming a thick oxide layer over fins for EG devices and a thinner oxide layer over fins for SG devices on the same substrate and the resulting device are provided. Embodiments include forming a first set of fins over a first portion of a Si substrate; forming a second set of fins over a second portion of the Si substrate spaced from the first portion; forming an iRAD SiO 2 layer over the first and second sets of fins; forming a polysilicon layer over the iRAD SiO 2 layer over the first set of fins; forming a radical SiO 2 layer over the iRAD SiO 2 layer over the second set of fins and over the polysilicon layer; forming a mask over the radical SiO 2 layer over the second set of fins; removing the polysilicon layer; and removing the mask and the iRAD SiO 2 layer from the first set of fins.

First claim

What is claimed is:

1. A method comprising:
forming a first set of fins over a first portion of a silicon (Si) substrate;
forming a second set of fins over a second portion of the Si substrate spaced from the first portion;
forming an iRAD silicon dioxide (SiO 2 ) layer over the first and second sets of fins;
forming a polysilicon layer over the iRAD SiO 2 layer over the first set of fins;
forming a radical SiO 2 layer over the iRAD SiO 2 layer over the second set of fins and over the polysilicon layer;
forming a mask over the radical SiO 2 layer over the second set of fins;
removing the polysilicon layer; and
removing the mask and the iRAD SiO 2 layer from the first set of fins.

2. The method according to claim 1 , comprising forming the polysilicon layer over the first set of fins by:
forming a polysilicon layer over the first and second sets of fins;
forming an optical planarization layer (OPL) and a silicon oxynitride (SiON) based anti reflective coating (SiARC) over the first set of fins;
removing the polysilicon from the second set of fins; and
removing the OPL and SiARC.

3. The method according to claim 1 , comprising forming the radical SiO 2 layer by low temperature radical oxidation.

4. The method according to claim 1 , comprising forming the mask by:
forming an OPL over the hardmask and the radical SiO 2 ;
forming a SiARC over the second set of fins; and
removing the OPL from the first set of fins.

5. The method according to claim 1 , comprising removing the radical SiO 2 from the first set of fins prior to removing the polysilicon layer.

6. The method according to claim 5 , comprising removing the radical SiO 2 by a buffered oxide etch (BOE).

7. The method according to claim 1 , wherein a pitch of the first set of fins is smaller than a pitch of the second set of fins.

8. The method according to claim 1 , comprising forming the IRAD SiO 2 layer to a thickness of 3 nanometer (nm) to 10 nm.

9. The method according to claim 8 , comprising forming the radical SiO 2 layer to a thickness of 3 nm to 10 nm.

10. A method comprising:
forming a first set of fins over a first portion of a silicon (Si) substrate;
forming a second set of fins over a second portion of the Si substrate separated from the first set of fins;
forming an iRAD silicon dioxide (SiO 2 ) layer over the first and second sets of fins;
forming a polysilicon layer over the iRAD SiO 2 layer over the first set of fins;
forming a radical SiO 2 layer over the iRAD SiO 2 layer over the second set of fins and over the polysilicon layer;
forming an optical planarization layer (OPL) over the radical SiO 2 layer over the second set of fins, to a height less than a height of the polysilicon layer;
removing the polysilicon layer; and
removing the OPL.

11. The method according to claim 10 , further comprising forming the OPL to height less than a height of the polysilicon by:
coating an OPL over the first and second sets of fins to a height above the height of the polysilicon; and
removing the OPL over the first set of fins and concurrently recessing the OPL over the second set of fins to a height below the height of the polysilicon.

12. The method according to claim 10 , comprising forming the polysilicon layer over the first set of fins by:
forming a polysilicon layer over the first and second sets of fins;
forming an OPL and a silicon oxynitride (SiON) based anti reflective coating (SiARC) over the first set of fins;
removing the polysilicon from the second set of fins; and
removing the OPL and SiARC.

13. The method according to claim 10 , comprising forming the radical SiO 2 layer by low temperature radical oxidation.

14. The method according to claim 10 , comprising removing the radical SiO 2 from the first set of fins prior to removing the polysilicon layer by a buffered oxide etch (BOE).

15. The method according to claim 10 , wherein a pitch of the first set of fins is smaller than a pitch of the second set of fins.

16. The method according to claim 10 , comprising forming the IRAD SiO 2 layer to a thickness of 3 nanometer (nm) to 10 nm.

17. The method according to claim 16 , comprising forming the radical SiO 2 layer to a thickness of 3 nm to 10 nm.

Assignees

• Globalfoundries Inc

Inventors

• Sung Min Gyu
• Park Chanro
• Kim Hoon
• Xie Ruilong

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H01L21/823462

  Electricity · mapped topic