Linear Stage for reflective electron beam lithography

Patent metadata

Field	Value
Publication number	US-9690213-B2
Application number	US-201213824079-A
Country	US
Kind code	B2
Filing date	Sep 6, 2012
Priority date	Sep 6, 2011
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A linear stacked stage suitable for REBL may include a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis, the first upper fast stage configured to secure a first plurality of wafers; a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and a carrier stage configured to translate the first and second upper fast stages along a second axis.

First claim

What is claimed:

1. A linear stacked stage, comprising:
a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis at a first selected speed, the first upper fast stage configured to secure the first plurality of wafers;
a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis at a second selected speed, the second upper fast stage configured to secure the second plurality of wafers, the second direction opposite to the first direction, wherein the translation of the first upper fast stage and the translation of the second upper fast stage are configured to substantially eliminate inertial reaction forces generated by motion of the first upper fast stage and the second upper fast stage; and
a carrier stage configured to translate the first upper fast stage and the second upper fast stage along a second axis substantially orthogonal to the first axis at a third selected speed, the first upper fast stage and the second upper fast stage disposed on the surface of the carrier stage, wherein the first upper fast stage, the second upper fast stage and the carrier stage are configured to scan one or more wafers of at least one of the first plurality of wafers or the second plurality of wafers under a plurality of electron columns,
wherein the third selected speed of the carrier stage is slower than the first selected speed of the first upper fast stage and the second selected speed of the second upper fast stage.

2. The stacked stage of claim 1 , further comprising:
a counter mass configured for translation along the second axis, wherein the counter mass is further configured to substantially counter inertial reaction forces generated by motion of the carrier stage.

3. The stacked stage of claim 1 , wherein at least one of the first upper fast stage and the second upper fast stage includes a long-stroke scanning stage.

4. The stacked stage of claim 3 , wherein the long-stroke scanning stage comprises:
a magnetic levitation stage.

5. The stacked stage of claim 4 , wherein the magnetic levitation stage comprises:
a set of variable reluctance actuators.

6. The stacked stage of claim 3 , wherein the long-stroke scanning stage comprises:
an air bearing stage.

7. The stacked stage of claim 1 , wherein at least one of the first upper fast stage and the second upper fast stage further includes a plurality of short-stroke scanning stages.

8. The stacked stage of claim 7 , wherein each of the short-stroke scanning stages comprise:
a magnetic levitation stage.

9. The stacked stage of claim 8 , wherein the magnetic levitation stage comprises:
a magnetic levitation stage controlled utilizing one or more Lorentz motors.

10. The stacked stage of claim 7 , wherein each of the short-stroke scanning stages is configured to translate a wafer along at least one a first axis, a second axis and a third axis, wherein the first axis, the second axis, and the third axis are mutually perpendicular.

11. The stacked stage of claim 7 , wherein each short-stroke scanning stage is equipped with an electrostatic chuck.

12. The stacked stage of claim 7 , wherein each short-stroke scanning stage is equipped with an interferometer based stage metrology system.

13. The stacked stage of claim 1 , wherein the carrier stage comprises:
at least one of a magnetic levitation stage, an air bearing stage, and a roller bearing stage.

14. The stacked stage of claim 1 , wherein the first upper fast stage and the second upper fast stage include magnetic shielding for shielding spatially fixed magnetic disturbances.

15. A linear stacked stage, comprising:
a first upper fast stage configured to translate a first plurality of wafers in a first direction along a first axis at a first selected speed, the first upper fast stage configured to secure the first plurality of wafers;
a second upper fast stage configured to translate a second plurality of wafers in a second direction along the first axis at a second selected speed, the second upper fast stage configured to secure the second plurality of wafers; and
a carrier stage configured to translate the first upper fast stage and the second upper fast stage along a second axis substantially orthogonal to the first axis at a third selected speed, the first upper fast stage and the second upper fast stage disposed on the surface of the carrier stage, wherein the first upper fast stage, the second upper fast stage and the carrier stage are configured to scan one or more wafers of at least one of the first plurality of wafers or the second plurality of wafers under a plurality of electron columns,
wherein the third selected speed of the carrier stage is slower than the first selected speed of the first upper fast stage and the second selected speed of the second upper fast stage.

16. The stacked stage of claim 15 , further comprising:
a counter mass configured for translation along at least one of the first axis and the second axis, wherein the translation of the counter mass is further configured to substantially counter inertial reaction forces generated by motion of the first upper fast stage, the second upper fast stage, and the carrier stage.

17. The stacked stage of claim 15 , wherein at least one of the first upper fast stage and the second upper fast stage includes a long-stroke scanning stage.

18. The stacked stage of claim 17 , wherein the long-stroke scanning stage comprises:
a magnetic levitation stage.

19. The stacked stage of claim 18 , wherein the magnetic levitation stage comprises:
a set of variable reluctance actuators.

20. The stacked stage of claim 17 , wherein the long-stroke scanning stage comprises:
an air bearing stage.

21. The stacked stage of claim 15 , wherein at least one of the first upper fast stage and the second upper fast stage further includes a plurality of short-stroke scanning stages.

22. The stacked stage of claim 21 , wherein each of the short-stroke scanning stages comprise:
a magnetic levitation stage.

23. The stacked stage of claim 22 , wherein the magnetic levitation stage comprises:
a magnetic levitation stage controlled utilizing one or more Lorentz motors.

24. The stacked stage of claim 21 , wherein each of the short-stroke scanning stages is configured to translate a wafer along at least one a first axis, a second axis and a third axis, wherein the first axis, the second axis, and the third axis are mutually perpendicular.

25. The stacked stage of claim 21 , wherein each short-stroke scanning stage is equipped with an electrostatic chuck.

26. The stacked stage of claim 21 , wherein each short-stroke scanning stage is equipped with an interferometer based stage metrology system.

27. The stacked stage of claim 15 , wherein the carrier stage comprises:
at least one of a magnetic levitation stage, an air bearing stage, and a roller bearing stage.

28. The stacked stage of claim 15 , wherein the first direction and the second direction are the same.

29. The stacked stage of claim 15 , wherein the first direction and the second direction are different.

30. The stacked stage of claim 15 , wherein the first upper fast stage and the second upper fast stage include magnetic shielding for shielding spatially fixed magnetic disturbances.

Assignees

• Ummethala Upendra
• Hale Layton
• Clyne Joshua
• Nayfeh Samir
• Williams Mark
• Di Regolo Joseph A
• Wilson Andrew
• Kla Tencor Corp

Inventors

• Ummethala Upendra
• Hale Layton
• Clyne Joshua
• Nayfeh Samir
• Williams Mark
• Di Regolo Joseph A
• Wilson Andrew

Classifications

• H01J2237/20221

  Translation · CPC title

• G03F7/70766

  Reaction force control means, e.g. countermass · CPC title

• H01J2237/31789

  Reflection mask · CPC title

• G03F7/70716 Primary

  Stages · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title