Half bridge power conversion circuits using GaN devices

Patent metadata

Field	Value
Publication number	US-9685869-B1
Application number	US-201615360123-A
Country	US
Kind code	B1
Filing date	Nov 23, 2016
Priority date	Sep 16, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

First claim

What is claimed is:

1. A half bridge circuit comprising:
a GaN-based low side circuit including:
a GaN-based low side switch having a low side switch control gate, a low side switch source and a low side switch drain, wherein the low side switch source is coupled to a ground and the low side switch drain is connected to a switch node; and
a GaN-based low side switch driver having an output coupled to the low side switch control gate;
a GaN-based high side circuit including:
a GaN-based high side switch having a high side control gate, a high side switch source and a high side switch drain, wherein the high side switch source is coupled to the switch node and the high side switch drain is coupled to a voltage source; and
a GaN-based high side switch driver having an output coupled to the high side switch control gate and an input coupled to a level shift circuit;
a blanking pulse circuit configured to generate a signal that controls a state of at least one of the GaN-based low side switch and the GaN-based high side switch;
a state storage device that is configured to change a stored state corresponding to on and off states of the GaN-based high side switch driver; and
an under voltage lock out circuit configured to prevent drive signals from reaching the input of the GaN-based high side switch driver when a circuit supply voltage is less than a threshold voltage.

2. The half bridge circuit of claim 1 wherein the blanking pulse circuit is configured to generate a pulse signal that corresponds to a turn off transient of the GaN-based low side switch to prevent turn-on of the GaN-based high side switch.

3. The half bridge circuit of claim 1 wherein the state storage device is a flip-flop device.

4. The half bridge circuit of claim 1 wherein the GaN-based low side circuit and the GaN-based high side circuit are disposed on a single monolithic GaN-based device.

5. The half bridge circuit of claim 1 wherein the GaN-based low side circuit is disposed on a first monolithic GaN-based device and the GaN-based high side circuit is disposed on a second monolithic GaN-based device.

6. The half bridge circuit of claim 1 further comprising a boot strap transistor configured to conduct when the GaN-based low side switch is in an on state.

7. The half bridge circuit of claim 1 wherein at least one of the GaN-based low side circuit and the GaN-based high side circuit have an ESD protection circuit.

8. The half bridge circuit of claim 1 wherein all transistors within the GaN-based low side circuit and within the GaN-based high side circuit are enhancement mode devices.

9. The half bridge circuit of claim 1 wherein all inverters and gates within the GaN-based low side circuit and within the GaN-based high side circuit are enhancement mode transistors.

10. The half bridge circuit of claim 1 wherein all inverters and gates within the GaN-based low side circuit and within the GaN-based high side circuit use charge pump capacitors to drive gates of pull-up transistors above a positive rail voltage.

11. A method of operating a half bridge power conversion circuit, the method comprising:
operating a low side switch using a low side driver, wherein the low side switch and the low side driver comprise a first GaN-based circuit;
operating a high side switch using a high side driver, wherein the high side switch and the high side driver comprise a second GaN-based circuit;
controlling the low side driver and the high side driver with a control circuit that transmits on and off signals to the low side and the high side drivers;
generating a blanking pulse to control a state of at least one of the GaN-based low side switch and the GaN-based high side switches;
changing a state of a state storage device corresponding to on and off states of the GaN-based high side switch driver;
transmitting a drive signal to an input of the high side driver with a level shift circuit; and
preventing the high side driver from operating the high side switch when a circuit supply voltage is less than a threshold voltage.

12. The method of claim 11 wherein the blanking pulse corresponds to a turn off transient of the GaN-based low side switch to prevent turn-on of the GaN-based high side switch.

13. The method of claim 11 wherein the state storage device is a flip-flop device.

14. The method of claim 11 wherein the GaN-based low side switch and the GaN-based high side switch are disposed on a single monolithic GaN-based device.

15. The method of claim 11 wherein the GaN-based low side switch is disposed on a first GaN-based device and the GaN-based high side switch is disposed on a second GaN-based device.

16. An electronic package including one or more semiconductor devices that form a circuit comprising:
a GaN-based low side circuit including:
a GaN-based low side switch having a low side switch control gate, a low side switch source and a low side switch drain, wherein the low side switch source is coupled to a ground and the low side switch drain is connected to a switch node; and
a GaN-based low side switch driver having an output coupled to the low side switch control gate;

a GaN-based high side circuit including:
a GaN-based high side switch having a high side control gate, a high side switch source and a high side switch drain, wherein the high side switch source is coupled to the switch node and the high side switch drain is coupled to a voltage source; and
a GaN-based high side switch driver having an output coupled to the high side switch control gate and an input coupled to a level shift circuit;

a blanking pulse circuit configured to generate a signal that controls a state of at least one of the GaN-based low side switch and the GaN-based high side switch;
a state storage device that is configured to change a stored state corresponding to on and off states of the GaN-based high side switch driver; and
an under voltage lock out circuit configured to prevent drive signals from reaching the input of the GaN-based high side switch driver when a circuit supply voltage is less than a threshold voltage.

17. The electronic package of claim 16 wherein the blanking pulse circuit is configured to generate a pulse signal that corresponds to a turn off transient of the GaN-based low side switch to prevent turn-on of the GaN-based high side switch.

18. The electronic package of claim 16 wherein the state storage device is a flip-flop device.

19. The electronic package of claim 16 wherein the GaN-based low side circuit and the GaN-based high side circuit are disposed on a single monolithic GaN-based device.

20. The electronic package of claim 16 wherein the GaN-based low side circuit is disposed on a first GaN-based device and the GaN-based high side circuit is disposed on a second GaN-based device.

Assignees

• Navitas Semiconductor Inc

Inventors

• Kinzer Daniel M
• Sharma Santosh
• Zhang Ju Jason

Classifications

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/411 Primary

  Chip-supporting parts, e.g. die pads · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title