Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices

Patent metadata

Field	Value
Publication number	US-8970262-B2
Application number	US-201213978373-A
Country	US
Kind code	B2
Filing date	Jan 9, 2012
Priority date	Jan 7, 2011
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

First claim

The invention claimed is:

1. A semiconductor device arrangement, comprising:
a first transistor having a load path between load terminals and a control terminal configured to receive a drive voltage that switches on or switches off the first transistor;
a plurality of second transistors, each second transistor having a load path between a first load terminal and a second load terminal and a control terminal;
wherein the second transistors have their load paths connected in series and connected in series to the load path of the first transistor;
wherein each but one of the second transistors has its control terminal connected to the load terminal of another one of the second transistors;
wherein one of the second transistors has its control terminal connected to one of the load terminals of the first transistor; and
wherein the first transistor comprises a normally-off transistor.

2. The semiconductor device arrangement of claim 1 , wherein one of the second transistors that has its load path directly connected to the load path of the first transistor and has its control terminal connected to a first load terminal of the first transistor and wherein each of the other second transistors has its control terminal connected to a first load terminal of an adjacent second transistor.

3. The transistor arrangement of claim 1 , wherein the first transistor and/or one or more of the second transistors is one of a MOSFET, a MISFET, a MESFET, an IGBT, a JFET, a HEMT, a FINFET, or a nanotube device.

4. The semiconductor device arrangement of claim 1 , wherein the first transistor and/or the second transistors comprise one of the following materials or compositions thereof: Si, SiO, SiN, Ge, Ga, Al, GaAs, GaN, carbon, In, InP, SiC.

5. The semiconductor device of claim 1 , wherein the second transistors are normally-on transistors.

6. The semiconductor device arrangement of claim 1 , wherein the first transistor is one of an n-channel or p-channel transistor.

7. The semiconductor device arrangement of claim 1 , wherein the second transistors are one of n-channel or p-channel transistors.

8. The semiconductor device arrangement of claim 1 , wherein the first transistor and the second transistors are implemented in a common semiconductor body.

9. The semiconductor device arrangement of claim 1 , wherein the second transistors are implemented as FINFETs, each second transistor comprising:
a semiconductor fin;
a source region, a body region and a drain region arranged in the semiconductor fin, the body region being arranged between the source region and the drain region; and
a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.

10. The semiconductor device arrangement of claim 9 , wherein the source and drain regions are arranged distant in a longitudinal direction of the semiconductor fin.

11. The semiconductor device arrangement of claim 9 , wherein the semiconductor fin includes sidewalls and wherein the gate electrode is arranged at least on one of the sidewalls of the semiconductor fin.

12. The semiconductor device arrangement of claim 9 , wherein the semiconductor fin is arranged above a substrate.

13. The semiconductor device arrangement of claim 12 , wherein the substrate includes at least one semiconductor layer adjoining the body regions of the second transistors.

14. The semiconductor device arrangement of claim 12 , wherein the substrate includes a dielectric layer adjoining the body regions of the second transistors.

15. The semiconductor device arrangement of claim 9 , wherein the semiconductor fins of two neighboring second transistors are separated by an insulation layer.

16. The semiconductor device arrangement of claim 9 , wherein one FINFET further comprises:
a source electrode connected to the source region; and
a semiconductor region doped complementarily to the source region and connected to the source electrode.

17. The semiconductor arrangement of claim 9 , wherein the first transistor is implemented as a FINFET comprising:
at least one semiconductor fin;
a source region, a body region and a drain region arranged in the at least one semiconductor fin, the body region being arranged between the source region and the drain region; and
a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric.

18. The semiconductor device arrangement of claim 1 , further comprising at least one voltage limiting element connected in parallel with at least one second transistor and/or in parallel to the first transistor.

19. A method for operating a semiconductor device arrangement,
wherein the semiconductor device arrangement comprises:
a first transistor having a load path between load terminals and a control terminal configured to receive a drive voltage that switches on or switches off the first transistor;
a plurality of second transistors, each having a load path between a first load terminal and a second load terminal and a control terminal;
wherein the second transistors have their load paths connected in series and connected in series to the load path of the first transistor;
wherein each but one of the second transistors has its control terminal connected to the load terminal of another one of the second transistors;
wherein one of the second transistors has its control terminal connected to one of the load terminals of the first transistor; and

wherein the method comprises switching the semiconductor device arrangement on or switching the semiconductor device arrangement off by applying a drive potential to the control terminal of the first transistor.

20. The method of claim 19 , wherein the first transistor comprises a normally-off transistor.

21. A circuit arrangement comprising:
a transistor arrangement with a first transistor having a load path and a control terminal and with a plurality of second transistors, each second transistor having a load path between a first and a second load terminal and a control terminal, wherein the second transistors have their load paths connected in series and connected in series to the load path of the first transistor, and wherein each but one of the second transistors has its control terminal connected to the load terminal of another one of the second transistors, and wherein one of the second transistors has its control terminal connected to one of the load terminals of the first transistor; and
a capacitive storage element connected to the load terminal of one of the second transistors.

22. The circuit arrangement of claim 21 , further comprising a control circuit having an output terminal coupled to the control terminal of the first transistor and having supply terminals, wherein the capacitive storage element is connected to the supply terminals of the control circuit.

23. The circuit arrangement of claim 22 , wherein the control circuit is configured to provide a pulse-width modulated drive signal to the first transistor.

24. The circuit arrangement of claim 21 , further comprising a load connected in series with the transistor arrangement, the series circuit with the transistor arrangement and the load being connected between input terminals that are configured to have an input voltage applied thereto.

25. The circuit arrangement of claim 24 , wherein the load comprises:
a transformer with a first winding c

Assignees

• Weis Rolf
• Hirler Franz
• Feldtkeller Martin
• Deboy Gerald
• Stecher Matthias
• Willmeroth Armin
• Infineon Technologies Austria

Inventors

• Weis Rolf
• Hirler Franz
• Feldtkeller Martin
• Deboy Gerald
• Stecher Matthias
• Willmeroth Armin

Classifications

• H03K17/06

  Modifications for ensuring a fully conducting state · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/87

  of PN-junction gate FETs · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title