Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain

Patent metadata

Field	Value
Publication number	US-9685536-B2
Application number	US-201213407855-A
Country	US
Kind code	B2
Filing date	Feb 29, 2012
Priority date	Mar 23, 2001
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of mono crystalline silicon on the surface of a semi conductive substrate, and forming a thin film of insulative material over the epitaxial layer. A second epitaxial layer is selectively, grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface.

First claim

The invention claimed is:

1. A vertical transistor structure extending in a direction substantially normal to a semiconductive region of a substrate, comprising:
a vertical transistor gate region oriented in a vertical plane from the substrate surface, including at least two overlying layers of epitaxially grown silicon, each epitaxial layer comprising a single silicon crystal having a top or upper surface defining a facet;
a vertical transistor source including a diffusion region adjacent to said transistor gate region within the semiconductive region; and
a vertical transistor drain including a diffusion region adjacent to said transistor gate region within the semiconductive region.

2. The vertical transistor structure as in claim 1 , wherein said vertical transistor gate region has a plane orientation, and vertically-oriented and insulated sidewalls.

3. The vertical transistor structure as in claim 2 , wherein said vertical transistor source is an elevated structure extending in a vertical plane from the substrate.

4. The vertical transistor structure as in claim 3 , wherein said vertical transistor drain is an elevated structure extending in a vertical plane from the substrate.

5. The vertical transistor structure as in claim 1 , wherein said vertical transistor source is a vertical structure comprising multiple epitaxial layers having insulated sidewalls and an insulated top surface on the uppermost epitaxial layer.

6. The vertical transistor structure as in claim 5 , wherein said vertical transistor source is a vertical structure comprising multiple epitaxial layers having insulated sidewalls and an insulated top surface on the uppermost epitaxial layer.

7. The vertical transistor structure as in claim 2 , wherein said vertical transistor drain is buried within the semiconductive substrate; and said vertical transistor source comprises at least one layer of epitaxially grown silicon overlying the uppermost layer of said gate region doped with a conductivity enhancing dopant having insulated sidewalls and on top surface.

8. The vertical transistor structure as in claim 7 , wherein said vertical transistor drain comprises a doped area within the substrate underlying said vertical transistor gate region.

9. The vertical transistor structure as in claim 2 , wherein said vertical transistor source is buried within the semiconductive substrate; and said vertical transistor drain comprises at least one layer of epitaxially grown silicon overlying the uppermost layer of said vertical transistor gate region doped with a conductivity enhancing dopant having insulated sidewalls and on top surface.

10. The vertical transistor structure as in claim 9 , wherein said vertical transistor source comprises a doped area within the substrate underlying said vertical transistor gate region.

11. The vertical transistor structure as in claim 9 , further comprising a series of oxide layers on the sides of each of said layers of single epitaxially grown silicon crystal silicon to form an insulating sidewall.

Assignees

• Ping Er-Xuan
• Mckee Jeffrey A
• Conversant Intellectual Property Man Inc

Inventors

• Ping Er-Xuan
• Mckee Jeffrey A

Classifications

• H10P14/3441

  Conductivity type · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/432

  using selective deposition · CPC title

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title