Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain
US-9685536-B2 · Jun 20, 2017 · US
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Ping Er-Xuan patents
Ping Er-Xuan holds 4 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 4 |
| Recent patents | 0 |
| First publication | May 5, 2015 |
| Latest publication | Jun 20, 2017 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Method and system for three-dimensional (3D) structure fill
US-9530674-B2 · Dec 27, 2016 · US
Methods for epitaxial silicon growth
US-9217209-B2 · Dec 22, 2015 · US
Method of fabricating a gate-all-around word line for a vertical channel DRAM
US-9023723-B2 · May 5, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Vertical transistor having a vertical gate structure having a top or upper surface defining a facet formed between a vertical source and a vertical drain
US-9685536-B2 · Jun 20, 2017 · US
Method and system for three-dimensional (3D) structure fill
US-9530674-B2 · Dec 27, 2016 · US
Methods for epitaxial silicon growth
US-9217209-B2 · Dec 22, 2015 · US
Method of fabricating a gate-all-around word line for a vertical channel DRAM
US-9023723-B2 · May 5, 2015 · US
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Electricity | 3 |
| Chemistry & Metallurgy | 2 |